CHL8515 Datasheet, PDF (12/16 Pages) International Rectifier – High‐Efficiency Variable Gate MOSFET Driver

High‐Efficiency Variable Gate MOSFET Driver _CHL8515
This startup also ensures that any undetermined PWM
signal levels from a controller in pre‐POR state will not
result in high‐ or low‐side MOSFET turn on until the
controller is out of its POR.
HIGH‐SIDE DRIVER
The high‐side driver drives an external floating N‐channel
MOSFET which can be switched at 1MHz. An external
bootstrap circuit referenced to the SWITCH node,
consisting of a boot diode and capacitor is used to bias
the external MOSFET gate. When the SWITCH node is at
ground, the boot capacitor is charged to near the supply
voltage using the boot diode and this stored charge is used
to turn on the external MOSFET when the PWM signal goes
high. Once the high‐side MOSFET is turned on, the SWITCH
voltage raises to the supply voltage and the boot voltage to
twice the supply voltage.
When the PWM signal goes low, the MOSFET is turned off
by pulling the MOSFET gate to the SWITCH voltage.
LOW‐SIDE DRIVER
The CHL8515 low‐side driver is designed to drive an
external N‐channel MOSFET referenced to ground at
1MHz. The low‐side driver is connected internally to the
supply voltage to turn the MOSFET on.
When the low‐side MOSFET is turned on the SWITCH
node is pulled to ground. This allows charging of the boot
capacitor to the supply voltage ready to drive the high‐side
MOSFET based on the PWM signal level.
ADAPTIVE DEAD TIME ADJUSTMENT
In a synchronous buck configuration dead time between
the turn off of one gate and turn on of the other is
necessary to prevent simultaneous conduction of the
external MOSFETS. It prevents a shoot‐through condition
which would result in a short of the supply voltage to
ground. A fixed dead time does not provide optimal
performance over a variety of MOSFETs, converter duty
cycles and board layouts.
The CHL8515 provides an ‘adaptive’ dead time adjustment.
This feature minimizes dead time to an optimum duration
which allows for maximum efficiency. The ‘break before
make’ adaptive design is achieved by monitoring gate and
SWITCH voltages to determine OFF status of a MOSFET.
It also provides zero‐voltage switching (ZVS) of the low‐
side MOSFET with minimum current conduction through
its body‐diode.
When the PWM is switching between 1.8V and 0V, its
falling edge transition from high to low will turn off the
high‐side gate driver. The adaptive dead time circuit
monitors the HI_GATE and the SWITCH node voltages
during the high‐side MOSFET turn off. When the HI_GATE
falls below 1.7V above the SWITCH node potential or the
SWITCH node voltage drops below 0.8V the high‐side
MOSFET is determined to be turned off and the LO_GATE
turn on is initiated. This turns on the external low‐side
MOSFET. The rising edge transition of the PWM signal from
low to high voltage causes the low‐side gate driver to turn
off. The adaptive circuit monitors the voltage at LO_GATE
and when it falls below 1.7V, the low‐side MOSFET is
determined to be turned off and the high‐side MOSFET
turn on is initiated.
12 December 6, 2011 | FINAL | V1.05