IR3500V Datasheet, PDF (10/34 Pages) International Rectifier – XPHASE3TM VR11.1 CPU VTT CONTROL IC

IR3500V
Figure 5 - Frequency variation with ROSC
This arrangement guarantees the error amplifier is always in control and can demand 0 to 100% duty cycle as
required. It also favors response to a load step decrease which is appropriate given the low output to input voltage
ratio of most systems. The inductor current will increase much more rapidly than decrease in response to load
transients. An additional advantage of the architecture is that differences in ground or input voltage at the phases
have no effect on operation since the PWM ramps are referenced to VDAC. The error amplifier is a high speed
amplifier with 110 dB of open loop gain. It is not unity gain stable. Figure 6 depicts PWM operating waveforms
under various conditions.
PHASE IC
CLOCK
PULSE
EAIN
PWMRMP
VDAC
GATEH
GATEL
STEADY-STATE
OPERATION
Page 10 of 34
DUTY CYCLE INCREASE
DUE TO LOAD
INCREASE
DUTY CYCLE DECREASE
DUE TO VIN INCREASE
(FEED-FORWARD)
DUTY CYCLE DECREASE DUE TO LOAD
DECREASE (BODY BRAKING) OR FAULT
(VCC UV, OCP, VID FAULT)
Figure 6 - PWM Operating Waveforms
STEADY-STATE
OPERATION
July 28, 2008