English
Language : 

IR3623MPBF Datasheet, PDF (1/26 Pages) International Rectifier – HIGH FREQUENCY 2-PHASE, SINGLE OR DUAL OUTPUT SYNCHRONOUS STEP DOWN CONTROLLER WITH OUTPUT TRACKING AND SEQUENCING
Data Sheet No.PD94717 revC
IR3623MPbF
HIGH FREQUENCY 2-PHASE, SINGLE OR DUAL OUTPUT SYNCHRONOUS STEP
DOWN CONTROLLER WITH OUTPUT TRACKING AND SEQUENCING
Features
Description
• Dual Synchronous Controller with 180o Out of Phase The IR3623 IC integrates a dual synchronous
Operation
Buck controller, along with IP2003A it is providing
• Configurable to 2-Independent Outputs or Current a high performance and flexible solution. The
Share Single Output
IR3623 can be configured as 2-independent
• Output Voltage Tracking
• Power up /down Sequencing
• Current Sharing Using Inductor’s DCR
outputs or as current share single output. The
current share configuration is ideal for high
current applications.
• +/-1% Accurate Reference Voltage
IR3623 enables output tracking and sequencing
• Programmable Switching Frequency up 1200kHz
• Programmable Over Current Protection
of multiple rails in either ratiometric or
simultaneous fashion. The IR3623 features 180o
• Hiccup Current Limit Using MOSFET RDS(on)
sensing
out of phase operation which reduces the
required input/output capacitance and results to
• Latched Overvoltage Protection
few number of capacitor quantity. The switching
• Dual Programmable Soft-Starts
frequency is programmable from 200kHz to
• Enable
• Pre-Bias Start-up
• Dual Power Good Outputs
• On Board Regulator
• External Frequency Synchronization
• Thermal Protection
• 32-Lead MLPQ Package
Applications
1200kHz per phase using one external resistor, in
addition IR3623 also allows the switching
frequency to be synchronized to an external clock
signal. Other key features offered by this device
include two independent programmable soft
starts, two independent power good outputs,
precision enable input and under voltage lockout
function. The current limit is provided by sensing
the lower MOSFET's on-resistance for optimum
• Embedded Telecom Systems
cost and performance. The output voltages are
• Distributed Point of Load Power Architectures
monitored through dedicated pins protect against
• Computing Peripheral Voltage Regulator
open circuit and enhance faster response to an
• Graphics Card
overvoltage event.
• General DC/DC Converters
12V
Vo1
Vo1
C1
Vout1
R10
R11
R1
C2 R2
C3 R3
OVP_Output
PGood1,2
C4
C5
5V_sns VOUT3
Vcc
Enable
Seq
Track1
Sync
Track2
Ph_En1
PWM1
VP1
OCSet1
VREF
VP2
IR3623
Vsns1
Rt
Fb1
Fb2
Comp1
Vsns2
Comp2
OCSet2
OVP_Output
PGood1,2
SS1 / SD
SS2 / SD
SGnd
Ph_En2
PWM2
OCGnd
Gnd
C6
R4 SW1
Vsns1
Fb1
Fb2
Vsns2
R5 SW2
Vdd
Vin
Enable1
IP2003A
PWM1
SW1
PRDY1
Gnd
PGnd
12V
Vdd
Vin
PRDY2
Enable2
PWM2
SW2
PGnd IP2003A
Gnd
C7
L1
R6
Vsns1
R7
R6
Fb1
R7
C8
L2
R8
Vsns2
R9
R8
Fb2
R9
Vout1
C9
Vout2
C10
Vo2
Vo2
Ratiometric Powerup Ratiometric Powerdown
Vo1
Vo1
Vo2
Vo2
Simultaneous Powerup Simultaneous Powerdown
Fig. 1: Power Up /Down Sequencing
ORDERING INFORMATION
PKG PACKAGE
DESIG DESCRIPTION
M
IR3623MPbF
M
IR3623MTRPbF
PIN
COUNT
32
32
PARTS
PER TUBE
73
--------
PARTS
PER REEL
-------
6000
T&R
ORIANTAION
Fig A
www.irf.com