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IR3564A Datasheet, PDF (1/4 Pages) International Rectifier – Dual Output Digital Multi-Phase Controller | |||
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IR3564A
Dual Output Digital Multi-Phase Controller IR3570A
FEATURES
ï· Dual output 4+1 and 3+2 phase PWM Controllers
ï· Easiest layout and fewest pins in the industry
ï· Fully supports AMD® SVI1 & SVI2 with dual OCP
and Intel® VR12 & VR12.5
ï· Overclocking & Gaming Mode
ï· Switching frequency from 200kHz to 2MHz
per phase
ï· IR Efficiency Shaping Features including
Dynamic Phase Control and Automatic Power
State Switching
ï· Programmable 1-phase or 2-phase operation for
Light Loads and Active Diode Emulation for Very
Light Loads
ï· IR Adaptive Transient Algorithm (ATA) on both
loops minimizes output bulk capacitors and
system cost
ï· Auto-Phase Detection with auto-compensation
ï· Per-Loop Fault Protection: OVP, UVP, OCP,
OTP, CFP
ï· I2C/SMBus/PMBus system interface for telemetry
of Temperature, Voltage, Current & Power for
both loops
ï· Multiple Time Programming (MTP) with
integrated charge pump for easy custom
configuration
ï· Compatible with IR ATL and 3.3V tri-state Drivers
ï· +3.3V supply voltage; -40°C to 85°C ambient
operation
ï· Pb-Free, RoHS, 5x5mm, 40-pin, 0.4mm pitch QFN
BASIC APPLICATION
VR_RDY_L1
VR_RDY_L2
VR_HOT#
ENABLE
SVC
SVD
SVT/ALERT#
3.3V
IR3570A
VR_RDY_L1 PWM1
VR_RDY_L2 ISEN1
VR_HOT# IRTN1
ENABLE
SVC
PWM3
ISEN3
IRTN3
SVD
PWM1_L2
SVT/ALERT#
ISEN1_L2
IRTN1_L2
VCC
PWM2_L2
ISEN2_L2
IRTN2_L2
Power
Stage 1
...
Power
Stage 3
Power
Stage 4
Power
Stage 5
12V
VOUT1
VOUT2
Figure 1: IR3564A/70A Basic Application Circuit
DESCRIPTION
The IR3564A/70A is a dual-loop digital multi-phase buck
controller designed for CPU voltage regulation and is fully
compliant with AMD® SVI1 & SVI2 and Intel® VR12 & VR12.5
specifications.
The IR3564A/70A includes IRâs Efficiency Shaping Technology
to deliver exceptional efficiency at minimum cost across the
entire load range. IRâs Dynamic Phase Control adds/drops
active phases based upon load current and can be configured
to enter 1-phase operation and diode emulation mode
automatically or by command.
IRâs unique Adaptive Transient Algorithm (ATA), based on
proprietary non-linear digital PWM algorithms, minimizes
output bulk capacitors and Multiple Time Programmable
(MTP) storage saves pins and enables a small package size.
Device configuration and fault parameters are easily defined
using the IR Digital Power Design Center (DPDC) GUI and
stored in on-chip MTP.
The IR3564A/70A provides extensive OVP, UVP, OCP and OTP
fault protection and includes thermistor based temperature
sensing with VRHOT signal.
The IR3564A/70A includes numerous features like register
diagnostics for fast design cycles and platform differentiation,
simplifying VRD design and enabling fastest time-to-market
(TTM) with âset-and-forgetâ methodology.
APPLICATIONS
ï· AMD® SVI1 & SVI2, Intel® VR12 & VR12.5 based systems
ï· Desktop & Notebook CPU VRs
ï· GPU & Memory VRs
PIN DIAGRAM
40 39 38 37 36 35 34 33 32 31
RCSP 1
RCSM 2
VRDY2 3
VSEN 4
VRTN 5
RRES 6
TSEN1 7
IR3570A/IR3564A
40 Pin 5x5 QFN
Top View
V18A 8
PWRGD/
VRDY1
9
PWROK/EN_L2/ 10
INMODE
1 = IR3570A
2 = IR3564A
41 GND
11 12 13 14 15 16 17 18 19 20
30 RCSP_L2
29 RCSM_L2
28 VCC
27 VSEN_L2
26 VRTN_L2
25 PWM1_L2
24 PWM42/PWM2_L21
23 PWM3
22 PWM2
21 PWM1
Figure 2: IR3564A/70A Package Top View
1 August 9, 2012 | FINAL | Produc t Brief | V2.04
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