IP2003 Datasheet, PDF (1/9 Pages) International Rectifier – MULTIPHASE OPTIMIZED LGA POWER BLOCK

PD- 96922A
iP2003
Synchronous Buck
Multiphase Optimized LGA Power Block
Features:
Integrated Power Semiconductors, Drivers & Passives
• Full function multiphase building block
• Output current 40A continuous with no derating up to
T_PCB = 100°C and T_CASE = 100°C
• Operating frequency up to 1.0 MHz
• Efficient dual sided cooling
• Small footprint low profile (11mm x 11mm x 2.2mm) package
• Optimized for very low power losses
• LGA interface
• Ease of design
• Proprietary packaging enables ultra low Rth_{j-case top}
Description
iP2003 Power Block
The iP2003 is a fully optimized solution for high current synchronous buck multiphase applications.
Board space and design time are greatly reduced because most of the components required for each
phase of a typical discrete-based multiphase circuit are integrated into a single 11mm x 11mm x 2.2mm
power block. The only additional components required for a complete multiphase converter are a PWM IC, the
external inductors, and the input and output capacitors.
iPOWIR technology offers designers an innovative board space saving solution for applications
requiring high power densities. iPOWIR technology eases design for applications where component integration
offers benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for
layout, heat transfer and component selection.
iP2003 Internal Block Diagram
P RDY
ENABLE
PWM
V_DD
SGND
MOSFET
Driver with
dead time
cont ro l
www.irf.com
V_IN
V_SW
P GND
Pin #
1
2
3
4
5, 7
6
8
11/18/04
Pin Name Pin Function
V_DD Supply voltage for the internal circuitry.
When set to logic level high, internal circuitry
of the device is enabled. When set to logic
ENABLE level low, the PRDY pin is forced low, the
Control and Sychronous switches are turned
off, and the supply current is less than 10µA.
PWM TTL-level input signal to MOSFET drivers.
PRDY
Power Ready - This pin indicates the status of
ENABLE or V_DD. This output will be driven
low when ENABLE is logic low or when V_DD
is less than 4.4V (typ.). When ENABLE is
logic high and V_DD is greater than 4.4V (typ.),
this output is driven high. This output has a
10mA source and 1mA sink capability.
PGND
V_SW
V_IN
Power Ground - connection to the ground of
bulk and filter capacitors.
Switching Node - connection to the output
inductor.
Input voltage for the DC-DC converter.
1