IP1203PBF Datasheet, PDF (1/23 Pages) International Rectifier – Single Output Full Function Synchronous Buck Power Block

PD- 97108
iP1203PbF
Features
• 5.5V to 13.2V Input Voltage
• 0.8V to 8V Output Voltage
• 15A Maximum Load Capability
• 200-400kHz Nominal Switching Frequency
• Over Current Hiccup
• External Synchronization Capable
• Overvoltage Protection
• Over Temperature Protection
• Internal Features Minimize Layout Sensitivity
• Very Small Outline 9mm x 9mm x 2.3mm
Single Output Full Function
Synchronous Buck Power Block
Integrated Power Semiconductors,
PWM Control & Passives
iP1203PbF Power Block
Description
The iP1203PbF is a fully optimized solution for medium current synchronous buck applications requiring up to
15A. It includes full function PWM control, with optimized power semiconductor chipsets and associated
passives, achieving high power density. Very few external components are required to create a complete
synchronous buck power supply.
iPOWIR™ technology offers designers an innovative space-saving solution for applications requiring high
power densities. iPOWIR technology eases design for applications where component integration offers benefits
in performance and functionality. iPOWIR technology solutions are also optimized internally for layout, heat
transfer and component selection.
iP1203PbF Simplified Application Schematic
V_IN
V_IN
OC
V_{CC_bypass}
VSW
FB
V_OUT
FB_S
SPGSOODiP^iP1¹2²0⁰3³PbF
Pin Number
(See Page 18) Pin Name
1, 23
V_IN
Pin Description
Input voltage connection pins
2,3,4,5,7,17,20,21 PGND
Power Ground pins
6
V_{CC_bypass}
PWM controller power supply pin. Internally generated.
Requires a 2.2µf external bypass capacitor
8
SS
Soft start pin. External capacitor provides soft start. Pulling soft start pin low
will disable the output. Cannot be cycled to unlatch OVP trip
9
CC
Output of the error amplifier
10
FB
Inverting input of the error amplifier
11
CC
12
R_T
13
SYNC
V
REF
14
15
PACKAGE
DESCRIPTION
PARTS
INTERFACE PARTS PER _PER
CONNECTION
BAG
REEL
iP1203PbF
LGA
10
---
iP1203TRPbF LGA
--- 1000
16
T&R
ORIENTATION
18,19
22
Fig 26
24
8/11/06
FB_s
Output overvoltage sense pin.
R_T
Switching frequency setting pin. For R_T selection, refer to Fig.9 of the
datasheet
Power Good pin. Open collector, requires external pulll-up. If function not
PGOOD
needed, pin can be left floating
V_REF
Non inverting input of the error amplifier (reference Voltage pin). Connect a
100pF cap from this pin to PGND.
SYNC
External Clock synchronization pin. Set free running frequency to 80% of
the SYNC frequency. When not in use, leave pin floating
OCSET
Output overcurrent trip threshold pin
V_SW
V_SWs
V_INs
Output inductor connection pins
Test pad, for internal use, short to VSW
Test pad, for internal use, short to V_IN