CHL8225G_15 Datasheet, PDF (1/3 Pages) International Rectifier – Digital Multi-Phase Buck Controller

Digital Multi-Phase Buck Controller CHL8225G/8G
FEATURES
 5-phase & 8-phase dual output PWM Controller
with phases flexibly assigned between Loops 1 & 2
 Dynamic voltage control by 2-bit parallel interface
with Gamer Mode override and Vmax setting
 Input Voltage Management for up to 3 Input
Voltages
 ICRITICAL Monitor and Phase Current Capture Mode
 Phase Switching frequency from 200kHz to 1.2MHz
 IR Efficiency Shaping Features including Variable
Gate Drive, Dynamic Phase Control
 Programmable 1-phase or 2-phase for Light Loads
and Active Diode Emulation for Very Light Loads
 IR Adaptive Transient Algorithm (ATA) minimizes
output bulk capacitors and system cost
 Per-Loop Fault Protection: OVP, UVP, OCP, OTP
 I2C/SMBus/PMBus system interface for telemetry of
Temperature, Voltage, Current & Power for both
loops
 Non-Volatile Memory (NVM) for custom
configuration
 Compatible with IR ATL and 3.3V tri-state Drivers
 +3.3V supply voltage; 0ºC to 85ºC ambient
operation
 Pb-Free, RoHS, 6x6 40-pin & 8x8 56-pin QFN, MSL2
package
APPLICATIONS
 Multiphase GPU systems
DESCRIPTION
The CHL8225G/8G are dual-loop, digital multi-phase buck
controllers. The CHL8225G drives up to 5 phases and the
CHL8228G drives up to 8 phases. They feature Input
Voltage Management allowing up to 3 input voltages to be
monitored to ensure adequate power is delivered to the
load. Dynamic voltage control is provided by 4 registers
which are programmed through I2C/SMBus/PMBus and
then selected using a 2-bit parallel bus for fast access.
The CHL8225G/8G includes the IR Efficiency Shaping
Technology to deliver exceptional efficiency at minimum
cost across the entire load range. IR Variable Gate Drive
optimizes the MOSFET gate drive voltage as a function of
real-time load current. IR Dynamic Phase Control adds and
drops phases based upon load current. The CHL8225G/8G
can be configured to enter 1-phase operation and active
diode emulation based upon load current or by command.
IR’s unique Adaptive Transient Algorithm (ATA), based on
proprietary non-linear digital PWM algorithms, minimizes
output bulk capacitors.
The I2C/PMBus interface can communicate with up to 16
CHL8225G/8G-based VR loops. Device configuration and
fault parameters are defined using the IR Digital Power
Design Center (DPDC) GUI and stored in on-chip NVM.
The CHL8225G/8G provides extensive OVP, UVP, OCP and
OTP fault protection and includes thermistor based
temperature sensing with VRHOT signal. The CHL8225G/8G
includes numerous features like register diagnostics for
fast design cycles and platform differentiation, simplifying
VRD design and enabling fastest time-to-market with its
“set-and-forget” methodology.
PIN DIAGRAM
40 39 38 37 36 35 34 33 32 31
RCSP 1
RCSM 2
VCC 3
VSEN 4
VRTN 5
RRES 6
TSEN 7
V18A 8
VR_READY_L1 9
VR_READY_L2 10
CHL8225G
40 Pin 6x6 QFN
Top View
41 GND
30 RCSP_L2
29 RCSM_L2
28 VCC
27 VSEN_L2
26 VRTN_L2
25 PWM5
24 PWM4
23 PWM3
22 PWM2
21 PWM1
11 12 13 14 15 16 17 18 19 20
56 55 54 53 52 51 50 49 48 47 46 45 44 43
ISEN8 1
RCSP 2
RCSM 3
VCC 4
VRHOT2 5
VSEN 6
VRTN 7
RRES 8
TSEN 9
V18A 10
VR_READY_L1 11
VR_READY_L2 12
EN_L2 13
VINSEN 14
CHL8228G
56 Pin 8x8 QFN
Top View
57 GND
42 ISEN7
41 RCSP_L2
40 RCSM_L2
39 VCC
38 VSEN_L2
37 VRTN_L2
36 PWM8
35 PWM7
34 PWM6
33 PWM5
32 PWM4
31 PWM3
30 PWM2
29 PWM1
15 16 17 18 19 20 21 22 23 24 25 26 27 28
Figure 1: CHL8225G Package Top View
1 June 21, 2013 | FINAL | V1.12
Figure 2: CHL8228G Package Top View