CHL8203_15 Datasheet, PDF (1/2 Pages) International Rectifier – Digital Multi-Phase Buck Controller

Digital Multi-Phase Buck Controller _{CHL8203/12/13/14}
FEATURES
 Dual output 2/3/4+1-phase PWM Controller
(CHL8212/13/14) and single output 3-phase PWM
Controller (CHL8203)
 Easiest layout and fewest pins in the industry
 Footprint compatible with CHL8225 (CHL8213/14)
for analog and power signals
 Up to 3 VID select lines for dynamic voltage
transitions
 Slow OCP for Thermal Design Current (TDC)
protection
 Programmable I_CRITICAL signal
 I2C interface for configuration & telemetry
 Pin programmable I2C address (CHL8203/13/14)
 Overclocking support with I2C voltage override and
Vmax setting
 Flexible I2C bus security features
 I2C security enable pin (CHL8203/13/14)
 Independent loop switching frequencies from 200kHz
to 1.2MHz per phase
 IR Efficiency Shaping with Dynamic Phase Control
(DPC)
 1-phase & Active Diode Emulation modes for light
load efficiency
 IR Adaptive Transient Algorithm (ATA) on both loops
minimizes output bulk capacitors and system cost
 Per-Loop Fault Protection: OVP, UVP, OCP
 Thermal Protection (OTP) and VRHOT# flag
(CHL8203/13/14)
 Multiple time programmable (MTP) memory for
custom configuration
 Compatible with IR ATL and 3.3V tri-state Drivers
 3.3V +10%/-15% supply voltage; 0ºC to 85ºC
operation
 Pb-Free, RoHS, QFN packages
APPLICATIONS
 Multi-phase GPU Systems
 GDDR Memory
DESCRIPTION
The CHL8212/13/14 are dual-loop digital multi-phase
buck controllers and the CHL8203 is a single-loop digital
multiphase buck controller designed for GPU voltage
regulation. Dynamic voltage control is provided by
registers which are programmed through I2C and then
selected using a 3-bit parallel bus for fast access.
The CHL8203/12/13/14 include IR Efficiency Shaping
Technology to deliver exceptional efficiency at minimum
cost across the entire load range. IR Dynamic Phase
Control adds/drops active phases based upon load current
and can be configured to enter 1-phase operation and
diode emulation mode automatically or by command.
IR’s unique Adaptive Transient Algorithm (ATA), based on
proprietary non-linear digital PWM algorithms, minimizes
output bulk capacitors and Multiple Time Programmable
(MTP) storage saves pins and enables a small package size.
Device configuration and fault parameters are easily
defined using the IR Digital Power Design Center (DPDC)
GUI and stored in on-chip MTP.
The CHL8203/12/13/14 provides extensive OVP, UVP, OCP
and OTP fault protection and the CHL8203/13/14 includes
thermistor based temperature sensing with VRHOT signal.
The CHL8203/12/13/14 includes numerous features like
register diagnostics for fast design cycles and platform
differentiation, truly simplifying VRD design and enabling
fastest time-to-market (TTM) with “set-and-forget”
methodology.
PIN DIAGRAM
40 39 38 37 36 35 34 33 32 31
RCSP 1
RCSM 2
VPGM2 3
VSEN 4
VRTN 5
RRES 6
TSEN1 7
V18A 8
VRRDY1 9
VRRDY2 10
CHL8213/4
40 Pin 6x6 QFN
Top View
1 _CHL8214
2 _CHL8213
41 GND
30 RCSP_L2
29 RCSM_L2
28 VCC
27 VSEN_L2
26 VRTN_L2
25 PWM_L2
24 PWM4¹/NC²
23 PWM3
22 PWM2
21 PWM1
11 12 13 14 15 16 17 18 19 20
1 August 28, 2013 | FINAL | V1.6
Figure 1: CHL8213/14 Package Top View