ISL89160_11 Datasheet, PDF (9/13 Pages) Intersil Corporation – High Speed, Dual Channel, 6A, 4.5 to 16VOUT, Power MOSFET Driver

ISL89160, ISL89161, ISL89162
Power Dissipation of the Driver
The power dissipation of the ISL89160, ISL89161, ISL89162 is
dominated by the losses associated with the gate charge of the
driven bridge FETs and the switching frequency. The internal bias
current also contributes to the total dissipation but is usually not
significant as compared to the gate charge losses.
12
10
V_DS = 64V
8
V_DS = 40V
6
4
2
0
0 2 4 6 8 10 12 14 16 18 20 22 24
Q_g, GATE CHARGE (nC)
FIGURE 16. MOSFET GATE CHARGE vs GATE VOLTAGE
Figure 16 illustrates how the gate charge varies with the gate
voltage in a typical power MOSFET. In this example, the total gate
charge for V_gs = 10V is 21.5nC when V_DS = 40V. This is the
charge that a driver must source to turn-on the MOSFET and
must sink to turn-off the MOSFET.
Equation 2 shows calculating the power dissipation of the driver:
P_D
=
2
•
Q_c
•
freq
•
V_GS
•
--------------^R----^g---^a----^t--^e---------------
R_gate + r_DS(ON)
+
I_DD(freq)
•
V_DD
(EQ. 2)
where:
freq = Switching frequency,
V_GS = V_DD bias of the ISL89160, ISL89161, ISL89162
Q_c = Gate charge for V_GS
I_DD(freq) = Bias current at the switching frequency (see Figure 9)
r_DS(ON) = ON-resistance of the driver
R_gate = External gate resistance (if any).
Note that the gate power dissipation is proportionally shared with
the external gate resistor and the output r_DS(ON). When sizing an
external gate resistor, do not overlook the power dissipated by
this resistor.
Typical Application Circuit
SQR
ZVS Full Bridge
V_bridge
PWM
L
R
L
LL
SQR
U1A
V_GUL
Q_UL
Q_UR
V_GUR
LR
V_LL
V_LR
V_GLL
V_GUL
V_GLR
VGUR
ISL89162
T1A
T2
U1B
Red dashed lines
QLL
emphasize the
V_GLL
resonant
switching delay ^LL
of the low-side
bridge FETs
U2A
½ ISL89160
LL: lower left
LR: lower right
UL: upper left
UR: upper right
GLL: gate lower left
Q_LR
V_GLR
T1B
LR
U2B
½ ISL89160
This is an example of how the ISL89160, ISL89161, ISL89162,
MOSFET drivers can be applied in a zero voltage switching full
bridge. Two main signals are required: a 50% duty cycle square
wave (SQR) and a PWM signal synchronized to the edges of the
SQR input. An ISL89162 is used to drive T1 with alternating half
cycles driving Q_UL and Q_UR. An ISL89160 is used to drive Q_LL and
Q_LR also with alternating half cycles. Unlike the two high-side
bridge FETs, the two low side bridge FETs are turned on with a
rising edge delay. The delay is setup by the RCD network on the
inputs to the ISL89160. The duration of the delay is chosen to
turn on the low-side FETs when the voltage on their respective
drains is at the resonant valley. For a complete description of the
ZVS topology, refer to AN1603 “ISL6752_54 Evaluation Board
Application Note”.
9
FN7719.1
January 20, 2011