ISL78100_15 Datasheet, PDF (9/19 Pages) Intersil Corporation – High Power LED Driver

ISL78100
Pin Descriptions
PIN
NAME
DESCRIPTION
1
VDC
Internally regulated 5V supply, tracks V_IN for input voltages less than 5V. LDO output can also be biased with
external supply if V_IN is <5.5V. A minimum of 3.3µF decoupling capacitor is needed in this pin.
2
VHI
Power FET gate drive supply. Can be biased with external supply if V_IN is <5.5V
3
OVP
Overvoltage monitor input; tie to VOUT for normal operation
4
SWD1
NMOS power FET drain
5
SWD2
NMOS power FET drain
6
BUCK/BOOSTN Tie to GND for BOOST operation and to VDC for Buck operation
7
LEVEL
Sets LED bias current level; VFB(nominal) = VLEVEL/5
8
TEMP
Temperature reference, tie to GND to disable temperature compensation
9
FB
LED current feedback
10
TMAX
Maximum LED temperature set point; if TEMP voltage exceeds TMAX, FB set point will be reduced
11
SWS2
NMOS power FET source
12
SWS1
NMOS power FET source
13
EN/PWM Chip enable and light modulation PWM dimming input
14
MODE
Digital Input; tie to GND to set FB reference to 400mV, tie to VDC to control FB reference with LEVEL input
15
ENL
LED load isolation MOS gate driver
16
VBAT
Input supply monitor
17
NC
Leave floating (internally connected)
18
GND
Ground return and FB ground reference
19
FAULT
Gate drive of fault protection FET. Driven low under fault conditions
20
VIN
Input supply
9
FN6626.1
December 24, 2013