ISL6622B Datasheet, PDF (9/11 Pages) Intersil Corporation – VR11.1 Compatible Synchronous Rectified Buck MOSFET Drivers

ISL6622B
• Minimize the inductance of the PHASE node: ideally, the
source of the upper and the drain of the lower MOSFET
should be as close as thermally allowable.
• Minimize the input current loop: connect the source of the
lower MOSFET to ground as close to the transistor pin as
feasible; input capacitors (especially ceramic decoupling)
should be placed as close to the drain of upper and source
of lower MOSFETs as possible.
In addition, for improved heat dissipation, place copper
underneath the IC whether it has an exposed pad or not. The
copper area can be extended beyond the bottom area of the
IC and/or connected to buried power ground plane(s) with
thermal vias. This combination of vias for vertical heat
escape, extended surface copper islands, and buried planes
combine to allow the IC and the power switches to achieve
their full thermal potential.
Upper MOSFET Self Turn-On Effect at Start-up
Should the driver have insufficient bias voltage applied, its
outputs are floating. If the input bus is energized at a high
dV/dt rate while the driver outputs are floating, due to self
coupling via the internal C_GD of the MOSFET, the gate of the
upper MOSFET could momentarily rise up to a level greater
than the threshold voltage of the device, potentially turning
on the upper switch. Therefore, if such a situation could
conceivably be encountered, it is a common practice to
place a resistor (R_UGPH) across the gate and source of the
upper MOSFET to suppress the Miller coupling effect. The
value of the resistor depends mainly on the input voltage’s
rate of rise, the C_GD/C_GS ratio, as well as the gate-source
threshold of the upper MOSFET. A higher dV/dt, a lower
C_DS/C_GS ratio, and a lower gate-source threshold upper
FET will require a smaller resistor to diminish the effect of
the internal capacitive coupling. For most applications, the
integrated 20kΩ resistor is sufficient, not affecting normal
performance and efficiency.
The coupling effect can be roughly estimated with Equation 5,
which assumes a fixed linear input ramp and neglects the
clamping effect of the body diode of the upper drive and the
bootstrap capacitor. Other parasitic components, such as lead
inductances and PCB capacitances, are also not taken into
account. Figure 7 provides a visual reference for this
phenomenon and its potential solution.
⎛
----------–---^V----^D-----^S-----------⎞
V_{G S _MILLER}
=
d_----V_---
dt
⋅
R
⋅
⎜
C _{r s s ⎜⎜} 1
–
d_----V_---
e ^dt
⋅
R
⋅
Cis
⎟
s⎟
⎟
⎜
⎟
⎝
⎠
(EQ. 5)
R = R_UGPH + R_GI
C_rss = C_GD
C_iss = C_GD + C_GS
UVCC
20kΩ
BOOT
C_BOOT
C_GD
VIN
D
UGATE
G
R_G
C_DS
C_GS
Q_UPPER
S
PHASE
FIGURE 7. GATE TO SOURCE RESISTOR TO REDUCE
UPPER MOSFET MILLER COUPLING
⎛
---------–----^V----^D-----^S-----------⎞
V _{G S _MILLER}
=
d_----V_---
dt
⋅
R
⋅
C_rs
s
⎜
⎜
⎜
1
–
e
d_----V_---
dt
⋅
R
⋅
Ci
s
⎟
s⎟
⎟
⎜
⎟
⎝
⎠
(EQ. 6)
R = R_UGPH + R_GI
C_rss = C_GD
C_iss = C_GD + C_GS
Gate Drive Voltage Options
Intersil provides various gate drive voltage options in the
ISL6622 product family, as shown in Table 2.
The ISL6622 can drop the low-side MOSFET’s gate drive
voltage when operating in DEM, while the high-side FET’s
gate drive voltage of the DFN package can be connected to
VCC or LVCC.
The ISL6622A allows the low-side MOSFET(s) to operate
from an externally-provided rail as low as 5V, eliminating the
LDO losses, while the high-side MOSFET’s gate drive voltage
of the DFN package can be connected to VCC or LVCC.
The ISL6622B sets the low-side MOSFET’s gate drive voltage
at a fixed, programmable LDO level, while the highside FETs’
gate drive voltage of the DFN package can be connected to
VCC or LVCC.
POWER RAILS
ISL6622
SOIC
DFN
ISL6622A SOIC
DFN
ISL6622B SOIC
DFN
TABLE 2. ISL6622 FAMILY OPTIONS
LVCC
PSI = LOW
PSI = HIGH
UVCC
5.75V
11.2V
VCC
Programmable
11.2V
Separate Rail
Separate Rail
VCC
Separate Rail
Separate Rail
5.75V
VCC
Programmable
Separate Rail
VCC
Operating Voltage Ranges from 6.8V to 13.2V
9
March 19, 2009