ISL6545 Datasheet, PDF (9/16 Pages) Intersil Corporation – 5V or 12V Single Synchronous Buck Pulse-Width Modulation (PWM) Controller

ISL6545, ISL6545A
Application” on page 3 for more detail; R_S is the upper
resistor; R_OFFSET (shortened to R_O below) is the lower one.
The recommended value for R_S is 1kΩ to 5kΩ (±1% for
accuracy) and then R_OFFSET is chosen according to the
equation below. Since R_S is part of the compensation circuit
(see Feedback Compensation section), it is often easier to
change R_OFFSET to change the output voltage; that way the
compensation calculations do not need to be repeated. If
V_OUT = 0.6V, then R_OFFSET can be left open. Output
voltages less than 0.6V are not available as shown in
Equation 2.
V_OUT=
0.6V •
(_---R_{----S-----+-----}R_-----O-----)
R_O
R_O
=
-----^R----^S-----^•----⁰----^.--⁶---^V-------
V_OUT – 0.6V
(EQ. 2)
Input Voltage Considerations
The Typical Application diagram on page 3 shows a
standard configuration where V_CC is either 5V (±10%) or
12V (±20%); in each case, the gate drivers use the V_CC
voltage for LGATE and BOOT/UGATE. In addition, V_CC is
allowed to work anywhere from 6.5V up to the 14.4V
maximum. The V_CC range between 5.5V and 6.5V is NOT
allowed for long-term reliability reasons, but transitions
through it to voltages above 6.5V are acceptable.
There is an internal 5V regulator for bias; it turns on between
5.5V and 6.5V; some of the delay after POR is there to allow
a typical power supply to ramp up past 6.5V before the
soft-start ramps begins. This prevents a disturbance on the
output, due to the internal regulator turning on or off. If the
transition is slow (not a step change), the disturbance should
be minimal. So while the recommendation is to not have the
output enabled during the transition through this region, it
may be acceptable. The user should monitor the output for
their application, to see if there is any problem.
The V_IN to the upper MOSFET can share the same supply
as V_CC, but can also run off a separate supply or other
sources, such as outputs of other regulators. If V_CC powers
up first, and the V_IN is not present by the time the
initialization is done, then the soft-start will not be able to
ramp the output, and the output will later follow part of the
V_IN ramp when it is applied. If this is not desired, then
change the sequencing of the supplies, or use the
COMP/SD pin to disable V_OUT until both supplies are ready.
Figure 6 shows a simple sequencer for this situation. If V_CC
powers up first, Q₁ will be off, and R₃ pulling to V_CC will turn
Q₂ on, keeping the ISL6545 in shut-down. When V_IN turns
on, the resistor divider R₁ and R₂ determines when Q₁ turns
on, which will turn off Q₂, and release the shut-down. If V_IN
powers up first, Q₁ will be on, turning Q₂ off; so the ISL6545
will start-up as soon as V_CC comes up. The V_DISABLE trip
point is 0.4V nominal, so a wide variety of NFET’s or NPN’s
or even some logic IC’s can be used as Q₁ or Q₂; but Q₂
must be low leakage when off (open-drain or open-collector)
so as not to interfere with the COMP output. Q₂ should also
be placed near the COMP/SD pin.
V_IN
V_CC
R₃
R₁
to COMP/SD
R₂
Q₁
Q₂
FIGURE 6. SEQUENCER CIRCUIT
The V_IN range can be as low as ~1V (for V_OUT as low as the
0.6V reference). It can be as high as 20V (for V_OUT just
below V_IN). There are some restrictions for running high V_IN
voltage.
The first consideration for high V_IN is the maximum BOOT
voltage of 36V. The V_IN (as seen on PHASE) plus V_CC (boot
voltage - minus the diode drop), plus any ringing (or other
transients) on the BOOT pin must be less than 36V. If V_IN is
20V, that limits V_CC plus ringing to 16V.
The second consideration for high V_IN is the maximum
(BOOT - V_CC) voltage; this must be less than 24V. Since
BOOT = V_IN + V_CC + ringing, that reduces to (V_IN + ringing)
must be <24V. So based on typical circuits, a 20V maximum
V_IN is a good starting assumption; the user should verify the
ringing in their particular application.
Another consideration for high V_IN is duty cycle. Very low
duty cycles (such as 20V in to 1.0V out, for 5% duty cycle)
require component selection compatible with that choice
(such as low r_DS(ON) lower MOSFET, and a good LC output
filter). At the other extreme (for example, 20V in to 12V out),
the upper MOSFET needs to be low r_DS(ON). In addition, if
the duty cycle gets too high, it can affect the overcurrent
sample time. In all cases, the input and output capacitors
and both MOSFETs must be rated for the voltages present.
Switching Frequency
The switching frequency is either a fixed 300kHz or 600kHz,
depending on the part number chosen (ISL6545 is 300kHz;
ISL6545A is 600kHz; the generic name “ISL6545” may apply
to either in the rest of this document, except when choosing
the frequency). However, all of the other timing mentioned
(POR delay, OCP sample, soft-start, etc.) is independent of
the clock frequency (unless otherwise noted).
BOOT Refresh
In the event that the UGATE is on for an extended period of
time, the charge on the boot capacitor can start to sag,
raising the r_DS(ON) of the upper MOSFET. The ISL6545 has
a circuit that detects a long UGATE on-time (nominal 100µs),
and forces the LGATE to go high for one clock cycle, which
will allow the boot capacitor some time to recharge.
Separately, the OCP circuit has an LGATE pulse stretcher
(to be sure the sample time is long enough), which can also
9
FN6305.5
April 29, 2010