ISL6439 Datasheet, PDF(9/15 Page) Intersil Corporation – Single Sync Buck PWM Controller for Broadband Gateway Applications

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ISL6439 Datasheet, PDF (9/15 Pages) Intersil Corporation – Single Sync Buck PWM Controller for Broadband Gateway Applications

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ISL6439, ISL6439A

that there is a path for the current to flow other than the

capacitance on the rail will prevent this failure mode.

Application Guidelines

Layout Considerations

Layout is very important in high frequency switching

converter design. With power devices switching efficiently at

300kHz or 600kHz, the resulting current transitions from one

device to another cause voltage spikes across the

interconnecting impedances and parasitic circuit elements.

These voltage spikes can degrade efficiency, radiate noise

into the circuit, and lead to device overvoltage stress.

Careful component layout and printed circuit board design

minimizes the voltage spikes in the converters.

As an example, consider the turn-off transition of the PWM

MOSFET. Prior to turn-off, the MOSFET is carrying the full load

current. During turn-off, current stops flowing in the MOSFET

and is picked up by the lower MOSFET. Any parasitic

inductance in the switched current path generates a large

voltage spike during the switching interval. Careful component

selection, tight layout of the critical components, and short, wide

traces minimizes the magnitude of voltage spikes.

There are two sets of critical components in a DC/DC

converter using the ISL6439. The switching components are

the most critical because they switch large amounts of

energy, and therefore tend to generate large amounts of

noise. Next are the small signal components which connect

to sensitive nodes or supply critical bypass current and

signal coupling.

A multi-layer printed circuit board is recommended. Figure 4

shows the connections of the critical components in the

converter. Note that capacitors CIN and COUT could each

represent numerous physical capacitors. Dedicate one solid

layer, usually a middle layer of the PC board, for a ground

plane and make all critical component ground connections

with vias to this layer. Dedicate another solid layer as a

power plane and break this plane into smaller islands of

common voltage levels. Keep the metal runs from the

PHASE terminals to the output inductor short. The power

plane should support the input power and output power

nodes. Use copper filled polygons on the top and bottom

circuit layers for the phase nodes. Use the remaining printed

circuit layers for small signal wiring. The wiring traces from

the GATE pins to the MOSFET gates should be kept short

and wide enough to easily handle the 1A of drive current.

The switching components should be placed close to the

ISL6439 first. Minimize the length of the connections between

the input capacitors, CIN, and the power switches by placing

them nearby. Position both the ceramic and bulk input

capacitors as close to the upper MOSFET drain as possible.

Position the output inductor and output capacitors between the

upper MOSFET and lower MOSFET and the load.

ISL6439

+3.3V VIN

VCC

CVCC

CPVOUT

CBP

GND

CIN

BOOT

UGATE

PHASE

LGATE

CBOOT

PHASE

LOUT

VOUT

COUT

COMP

R4 C3 R3

KEY

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT PLANE LAYER

VIA CONNECTION TO GROUND PLANE

FIGURE 4. PRINTED CIRCUIT BOARD POWER PLANES

AND ISLANDS

The critical small signal components include any bypass

capacitors, feedback components, and compensation

components. Position the bypass capacitor, CBP, close to

the VCC pin with a via directly to the ground plane. Place the

PWM converter compensation components close to the FB

and COMP pins. The feedback resistors for both regulators

should also be located as close as possible to the relevant

FB pin with vias tied straight to the ground plane as required.

Feedback Compensation

Figure 5 highlights the voltage-mode control loop for a

synchronous-rectified buck converter. The output voltage

(VOUT) is regulated to the Reference voltage level. The

error amplifier (Error Amp) output (VE/A) is compared with

the oscillator (OSC) triangular wave to provide a pulse-

width modulated (PWM) wave with an amplitude of VIN at

the PHASE node. The PWM wave is smoothed by the output

filter (LO and CO).

The modulator transfer function is the small-signal transfer

function of VOUT/VE/A. This function is dominated by a DC

Gain and the output filter (LO and CO), with a double pole

break frequency at FLC and a zero at FESR. The DC Gain of

FN9057.5

November 5, 2008

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