ISL6421 Datasheet, PDF (9/10 Pages) Intersil Corporation – Single Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-top Box Designs

ISL6421
TABLE 5. SYSTEM REGISTER (SR1 AND SR2) CONFIGURATION (Continued)
SR
DCL ISEL1 ENT1 LLC1 VSEL1 EN1 OLF1
FUNCTION
0
1
1
1
Dynamic current limit NOT selected
0
0
1
1
Dynamic current limit selected
0
X
1
X
X
X
0
PWM and Linear for channel 1 disabled
SR
-
-
-
-
EN2 OTF
1
X
X
X
X
0
X
Received Data (I²C Bus Read Mode)
The ISL6421 can provide to the master a copy of the System
Register information via the I²C bus in read mode. The read
mode is Master activated by sending the chip address with
R/W bit set to 1. At the following Master generated clock bits,
the ISL6421 issues a byte on the SDA data bus line (MSB
transmitted first).
At the ninth clock bit the MCU master can:
• Acknowledge the reception, starting in this way the
transmission of another byte from the ISL6421.
• Not acknowledge, stopping the read mode
communication.
While the whole register is read back by the microprocessor,
only the two read-only bits, OLF and OTF, convey diagnostic
information about the ISL6421.
TABLE 6. READING SYSTEM REGISTERS
DCL ISEL ENT LLC VSEL EN OTF OLF
FUNCTION
These bits are read as they were 0
after the last write operation.
Tj <= 130°C, Normal
operation
1
Tj > 150°C, Power
blocks disabled
0 Iout < Imax, Normal
operation
1 Iout > Imax, Overload
protection triggered
Power–On I²C Interface Reset
The I²C interface built into the ISL6421 is automatically reset
at power-on. The I²C interface block will receive a Power OK
logic signal from the UVLO circuit. This signal will go HIGH
when chip power is OK. As long as this signal is LOW, the
interface will not respond to any I²C commands and the
system register SR is initialized to all zeros, thus keeping the
power blocks disabled.
Once Vcc rises above the UVLO level, the POWER OK
signal given to the I²C interface block will be HIGH, the I²C
interface becomes operative and the SR can be configured
by the main microprocessor. About 400mV of hysteresis is
provided in the UVLO threshold to avoid false triggering of
the Power-On reset circuit.
-
FUNCTION
X SR2 is selected; to read OTF flag.
(I²C comes up with EN = 0, EN goes HIGH at the same time
as (or later than) all other I²C data for the PWM becomes
valid).
ADDRESS Pin
Connecting this pin to GND forces the chip I²C interface
address to 0001000; applying a voltage >2.7V forces the
address to 0001001, as shown below.
TABLE 7. ADDRESS PIN CHARACTERISTICS
VADDR
MIN
TYP
MAX
Vaddr-1
0V
“0001000”
-
2.0V
Vaddr-2
“0001001”
2.7V
-
5.0V
I²C Electrical Characteristics
TABLE 8. I²C SPECIFICATIONS
PARAMETER
TEST
CONDITION
MIN TYP
MAX
Input Logic High, SDA, SCL
VIH
0.7 x V_DD
Input Logic Low, SDA, SCL
VIL
0.3 x V_DD
Input Logic
Current, IIL
SDA, SCL;
0.4V < Vin < 4.5V
10µA
SCL Clock
Frequency
0 100kHz 400kHz
9