ISL54060_14 Datasheet, PDF (9/15 Pages) Intersil Corporation – Negative Signal Swing, Sub-ohm, Dual SPST Single Supply Swit

ISL54060, ISL54061
Test Circuits and Waveforms (Continued)
*50Ω SOURCE
V+
C
SIGNAL
GENERATOR
NO1 OR NC1 _COM1
50Ω
IN_X
0V OR V+
ANALYZER
COM2
NC2 OR NO2
NC
GND
R_L
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 5. CROSSTALK TEST CIRCUIT
IMPEDANCE
ANALYZER
V+
C
NO OR NC
IN 0V OR V+
COM
GND
COM is connected to NO or NC
during ON capacitance measurement.
FIGURE 6. CAPACITANCE TEST CIRCUIT
Detailed Description
The ISL54060 and ISL54061 are bidirectional, dual single
pole-single throw (SPST) analog switches that offers precise
switching from a single 1.8V to 6.5V supply with low
ON-resistance (0.83Ω) and high speed operation
(t_ON = 55ns, t_OFF = 18ns). The device is especially well
suited for portable battery powered equipment due to its low
operating supply voltage (1.8V), low power consumption
(8nA), and a tiny 1.8x1.4mm µTQFN package or a 3x3mm
TDFN package. The low ON-resistance and r_ON flatness
provide very low insertion loss and signal distortion for
applications that require signal switching with minimal
interference by the switch.
The ISL54060 is a normally open (NO) SPST analog switch.
The ISL54061 is a normally closed (NC) SPST analog
switch.
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. The ISL54060 and
ISL54061 contains ESD protection diodes on each pin of the
IC (see Figure 7). These diodes connect to either a +Ring or
-Ring for ESD protection. To prevent forward biasing the
ESD diodes to the +Ring, V+ must be applied before any
input signals, and the input signal voltages must remain
between recommended operating range.
If these conditions cannot be guaranteed, then precautions
must be implemented to prohibit the current and voltage at
the logic pin and signal pins from exceeding the maximum
ratings of the switch. The following two methods can be used
to provided additional protection to limit the current in the
event that the voltage at a logic pin or switch terminal goes
above the V+ rail.
Logic inputs can be protected by adding a 1kΩ resistor in
series with the logic input (see Figure 7). The resistor limits
the input current below the threshold that produces
permanent damage.
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low r_ON switch. Connecting external
Schottky diodes to the signal pins will shunt the fault current
to the V+ supply instead of through the internal ESD diodes
thereby protecting the switch. These Schottky diodes must
be sized to handle the expected fault current..
V+
+RING
V_COMx
CLAMP
V_NOx
OR
V_NCx
1kΩ
LOGIC
INPUTS
GND
-RING
FIGURE 7. OVERVOLTAGE PROTECTION
9
FN6580.2
November 3, 2009