ISL5314_05 Datasheet, PDF (9/16 Pages) Intersil Corporation – Direct Digital Synthesizer

ISL5314
Electrical Specifications
AV_DD = DV_DD =
all Min and Max
+5V (unless
Values. T_A =
o2t5h_oeCrwfoisreAnlloTteypdi)c, _{aVlRVEaFlu=esInt(}e_Crn_oa_nl_t1_in.2_uV_e,_dI₎OUTFS
=
20mA,
T_A
=
-40^oC
to
85^oC
for
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNITS
Address Hold Time, t_AH
UPDATE Pulse Width, t_UW
UPDATE Setup Time, t_US
UPDATE Hold Time, t_UH
UPDATE Latency, t_UL
Between ADDR and WR (Note 3)
(Note 3)
Between UPDATE and CLK (Note 3)
Between UPDATE and CLK (Note 3)
After UPDATE, before analog output change, if asserted after
writing to the control registers
0
-
5
-
1
-
3
-
-
14
-
ns
-
ns
-
ns
-
ns
-
Clock
Cycles
UPDATE Latency, t_UL
After UPDATE, before analog output change, if asserted before
-
11
-
Clock
writing to the control registers
Cycles
Maximum PH Rate
Phase Pulse Width, t_PW
Phase Setup Time, t_PS
Phase Hold Time, t_PH
Phase Latency, t_PL
Rate of PH1 and PH0 pins (Note 3)
PH(1:0) (Note 3)
Between PH(1:0) change and CLK (Note 3)
Between PH(1:0) change and CLK (Note 3)
Between PH(1:0) change and analog output change
f_CLK/2
-
5
-
1
-
3
-
-
12
-
Hz
-
ns
-
ns
-
ns
-
Clock
Cycles
Maximum ENOFR Rate
ENOFR Pulse Width, t_EW
ENOFR Setup Time, t_ES
ENOFR Hold Time, t_EH
ENOFR Latency, t_EL
Rate of ENOFR (Note 3)
ENOFR (Note 3)
Between ENOFR and CLK (Note 3)
Between ENOFR and CLK (Note 3)
After ENOFR, before analog output change
f_CLK/2
-
5
-
1
-
3
-
-
14
-
Hz
-
ns
-
ns
-
ns
-
Clock
Cycles
Write Enable Pulse Width, t_WR
Write Enable Setup Time, t_WS
Write Enable Hold Time, t_WH
RESET Pulse Width, t_RW
RESET Setup Time, t_RS
RESET Latency to Output, t_RL
WE (Note 3)
Between WE and WR (Note 3)
Between WE and WR (Note 3)
RESET (Note 3)
Between RESET and CLK
After RESET, before analog output reflects reset values
5
-
2
-
4
-
5
-
1
-
-
11
-
ns
-
ns
-
ns
-
ns
-
ns
-
Clock
Cycles
RESET Latency to Write, t_RE
After RESET, before the control registers can be written to
-
1
-
Clock
Cycles
Maximum SCLK Rate
See Figure 6 Timing Diagrams (Note 3)
50
-
-
MSPS
SCLK Pulse Width, t_SCW
SDATA Pulse Width, t_SDW
SDATA Setup Time, t_SDS
See Figure 6 Timing Diagrams (Note 3)
5
-
-
ns
See Figure 6 Timing Diagrams (Note 3)
5
-
-
ns
Between SDATA and SCLK. See Figure 6 Timing Diagrams. (Note 6
-
-
ns
3)
SDATA Hold Time, t_SDH
Between SDATA and SCLK. See Figure 6 Timing Diagrams. (Note 1
-
-
ns
3)
SSYNC Pulse Width, t_SSW
SSYNC Setup Time, t_SSS
See Figure 6 Timing Diagrams (Note 3)
5
-
-
ns
Between SSYNC and SCLK. See Figure 6 Timing Diagrams.
6
-
-
ns
(Note 3)
SSYNC Hold Time, t_SSH
Between SSYNC and SCLK. See Figure 6 Timing Diagrams.
1
-
-
ns
(Note 3)
9