ISL43841_04 Datasheet, PDF (9/14 Pages) Intersil Corporation – Low-Voltage, Single and Dual Supply, Dual 4 to 1 Multiplexer Analog Switch with Latch

ISL43841
Test Circuits and Waveforms (Continued)
V+
C
V-
C
LOGIC ^OFF
INPUT
ON
SWITCH
OUTPUT
V_OUT
Q = ∆V_OUT x C_L
3V
OFF
0V
∆V_OUT
R_G
LATCH
NO
COM
0Ω
ADD1, 2
V_G
GND
LOGIC
INPUT
FIGURE 2A. Q MEASUREMENT POINTS
Repeat test for other switches.
FIGURE 2B. Q TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
V_OUT
C_L
1nF
3V
LOGIC
INPUT
0V
SWITCH
OUTPUT
V_OUT
0V
t_r < 20ns
t_f < 20ns
t_BBM
80%
C
V+
LOGIC
INPUT
V+
C
V-
C
LATCH
NO0-NO3
ADD1, 2
COM
GND
V_OUT
R_L
300Ω
C_L
35pF
Repeat test for other switches. C_L includes fixture and stray
capacitance.
FIGURE 3A. t_BBM MEASUREMENT POINTS
FIGURE 3B. t_BBM TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
t_MPW
LOGIC ^3V
INPUT
LATCH
0V
50%
t_H
50%
t_S
LOGIC ^3V
INPUT
ADDX
0V
50%
VNO_X
SWITCH
OUTPUT
0V
V_OUT
t_r < 20ns
t_f < 20ns
50%
t_H
50%
t_ON, t_OFF
90%
Logic input waveform is inverted for switches that have the opposite
logic sense.
V+
V-
C
C
C
LOGIC
INPUT
LOGIC
INPUT
NO1-NO3
V+
ADD1, 2
NO0
LATCH
GND
V_OUT
COM
R_L
300Ω
C_L
35pF
Repeat test for other switches. C_L includes fixture and stray
capacitance.
V_OUT
=
V _(NO)
------------^R-----^L-------------
R_L + R_(ON)
FIGURE 4A. LATCH t_S, t_H, t_MPW MEASUREMENT POINTS
FIGURE 4B. LATCH t_S, t_H, t_MPW TEST CIRCUIT
FIGURE 4. LATCH SETUP AND HOLD TIMES
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