ISL29023_14 Datasheet, PDF (9/14 Pages) Intersil Corporation – Integrated Digital Light Sensor with Interrupt

ISL29023
OPERATION MODE BITS (B5 - B7)
ISL29023 has different operating modes. These modes are
selected by setting B5 - B7 bits on register address 0x00. The
device powers up on a disable mode. Table 6 lists the possible
operating modes.
TABLE 6. OPERATING MODES BITS
B7
B6
B5
OPERATION
0
0
0 Power-down the device (Default)
0
0
1 The IC measures ALS only once every
integration cycle. This is the lowest
operating mode.
0
1
0 IR once
0
1
1 Reserved (DO NOT USE)
1
0
0 Reserved (DO NOT USE)
1
0
1 The IC measures ALS continuously
1
1
0 The IC measures IR continuous
1
1
1 Reserved (DO NOT USE)
Command-II Register (Address: 0x01)
TABLE 7. COMMAND-II REGISTER BITS
NAME
Reg.
REGISTER BITS
Addr
(Hex) B7 B6 B5 B4 B3 B2 B1
DFLT
B0 (Hex)
COMMANDII 0x01 0 0 0 0 RES1 RES0 RANGE1 RANGE0 0x00
The Command-II register consists of two dynamic range bits, and
two DAC resolution bits. The default register value is 0x00 at
power-on.
FULL SCALE RANGE (B1-B0)
The Full Scale Range (FSR) has four different selectable ranges.
Each range has a maximum allowable lux value. Higher range
values offer wider ALS lux value. Table 8 lists the possible values
of FSR for the 499kΩ R_EXT resistor.
TABLE 8. RANGE REGISTER BITS
B0 B1 k
00 1
01 2
10 3
11 4
RANGE(k)
Range1
Range2
Range3
Range4
FSR (LUX) @ ALS
SENSING
1,000
4,000
16,000
64,000
FSR @ IR
SENSING
65535
65535
65535
65535
ADC RESOLUTION (B3 - B2)
B3 and B2 determine the ADC’s resolution and the number of
clock cycles per conversion. Changing the number of clock cycles
does more than just change the resolution of the device; it also
changes the integration time, which is the period the device’s
analog-to-digital (A/D) converter samples the photodiode current
signal for a measurement. The ONLY 16-bit ADC resolution is
capable of rejecting 50Hz and 60Hz flicker caused by artificial light
sources. Table 9 lists the possible ADC resolution.
.
B3
0
0
1
1
TABLE 9. ADC RESOLUTION DATA WIDTH
B2
NUMBER OF CLOCK CYCLES
0
2¹⁶ = 65,536
1
2¹² = 4,096
0
2⁸ = 256
1
2⁴ = 16
n-BIT ADC
16
12
8
4
Data Registers (Addresses: 0x02 and 0x03)
TABLE 10. ADC REGISTER BITS
Reg.
Register Bits
Addr
DFLT
NAME (Hex) B7 B6 B5 B4 B3 B2 B1 B0 (Hex)
DATA_LSB 0x02 D7 D6 D5 D4 D3 D2 D1 D0 0x00
DATA_MSB 0x03 D15 D14 D13 D12 D11 D10 D9 D8 0x00
The ISL29023 has two 8-bit read-only registers to hold the upper
and lower byte of the ADC value. The upper byte is accessed at
address 0x03 and the lower byte is accessed at address 0x02.
For 16-bit resolution, the data is from D0 to D15; for 12-bit
resolution, the data is from D0 to D11; for 8-bit resolution, the
data is from D0 to D7 and 4-bit resolution, the data is from D0 to
D3. The registers are refreshed after every conversion cycle. The
default register value is 0x00 at power-on.
TABLE 11. ADC DATA REGISTERS
ADDRESS
(hex)
CONTENTS
0x02 D0 is LSB for 4, 8, 12 or 16-bit resolution; D3 is MSB for
4-bit resolution; D7 is MSB for 8-bit resolution
0x03 D15 is MSB for 16-bit resolution; D11 is MSB for 12-bit
resolution
Lower Interrupt Threshold Registers
(Address: 0x04 and 0x05)
TABLE 12. INTERRUPT REGISTER BITS
NAME
Reg.
REGISTER BITS
Addr
DFLT
(Hex) B7 B6 B5 B4 B3 B2 B1 B0 (Hex)
INT_LT_LSB 0x04 TL7 TL6 TL5 TL4 TL3 TL2 TL1 TL0 0x00
INT_LT_MSB 0x05 TL15 TL14 TL13 TL12 TL11 TL10 TL9 TL8 0x00
The lower interrupt threshold registers are used to set the lower
trigger point for interrupt generation. If the ALS value crosses
below or is equal to the lower threshold, an interrupt is asserted
on the interrupt pin and the interrupt flag. Registers INT_LT_LSB
(0x04) and INT_LT_MSB (0x05) provide the low and high bytes,
respectively, of the lower interrupt threshold. The high and low
bytes from each set of registers are combined to form a 16-bit
threshold value. The interrupt threshold registers default to 0x00
upon power-up.
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FN6691.4
May 1, 2014