HSP45116-DB Datasheet, PDF (9/13 Pages) Intersil Corporation – HSP45116 Daughter Board

HSP45116-DB
TABLE 3. SIGNAL ASSIGNMENTS FOR 50 POSITION INPUT
CONNECTOR J1
PIN
NUMBER
J1A SIGNAL
MNEMONIC
J1B SIGNAL
MNEMONIC
1
N.C.
GND
2
RIN0
RIN1
3
RIN2
RIN3
4
RIN4
RIN5
5
RIN6
RIN7
6
GND
RIN8
7
RIN9
RIN10
8
RIN11
RIN12
9
RIN134
RIN14
10
RIN15
GND
11
N.C.
IMIN0
12
IMIN1
IMIN2
13
IMIN3
IMIN4
14
IMIN5
IMIN6
15
IMIN7
GND
16
IMIN8
IMIN9
17
IMIN10
IMIN11
18
IMIN12
IMIN13
19
IMIN14
IMIN15
20
GND
CLKIN
21
GND
N.C.
22
GND
V_CC
23
GND
V_CC
24
GND
V_CC
25
GND
V_CC
The J2 Output Header maps two 16-bit busses to the real
and imaginary outputs of the HSP45116, RO0-15 and IO0-
15. In addition, two HSP45116 status outputs, PACO and
TICO, two HSP45116 output enables, OER and OE, and a
bidirectional clock line are routed to this header as shown by
the signal map in Table 4. When mated with the J2
connector on the HSP-EVAL, the HSP45116's real and
imaginary outputs map to the HSP-EVAL's Output Bus 2 and
1, OUT2_0-15 and OUT1_0-15, respectively.
The J3 Control Header maps one 16-bit bus to the
HSP45116's control input, C0-15, and provides jumper
positions for the Configuration Jumper Fields that flank the
header. When mated with the HSP-EVAL's J3 Control
Connector the HSP45116's Control Inputs, C0-15, are
mapped to the HSP-EVAL's Input Bus 3, IN3_0-15, and the
jumper positions are mapped the HSP-EVAL's Control Bus,
CTL0-15. The signal map for the J3 Control Header is shown
in Table 1.
TABLE 4. SIGNAL ASSIGNMENTS FOR 50 POSITION OUT-
PUT CONNECTOR J2
PIN
NUMBER
J2A SIGNAL
MNEMONIC
J2B SIGNAL
MNEMONIC
1
OER
GND
2
RO0
RO1
3
RO2
RO3
4
RO4
RO5
5
RO6
RO7
6
GND
RO8
7
RO9
RO10
8
RO11
RO12
9
RO13
RO14
10
RO15
GND
11
OEI
IO0
12
IO1
IO2
13
IO3
IO4
14
IO5
IO6
15
IO7
GND
16
IO8
IO9
17
IO10
IO11
18
IO12
IO13
19
IO14
IO15
20
GND
CLKOUT
21
GND
TICO
22
GND
PACO
23
GND
N.C.
24
GND
N.C.
25
GND
N.C.
Configuration Jumper Field
The Configuration Jumper Fields A and B flank either side of
the Control Header J3 as shown in Table 1. Positions within
the Jumper Field's SA and SB signal rows map to various
HSP45116 control inputs. The control inputs may be
jumpered to ground or the HSP-EVAL's CTL4-15 bus via the
J3 Control Header. If a control signal mapped to SA and SB
is not jumpered to GND or CTL4-15, the signal is pulled
high.
The Configuration Jumper Field A is also used to select
whether the HSP45116's clock source is provided through
the J1 Input Header or the J2 Output Header. If jumpers are
inserted as shown in Figure 5, a clock signal supplied
through the CLK_IN pin of the J1 Input Header drives a
buffer whose output clocks the HSP45116. The jumper
inserted between JA1 and JA2 feeds the buffered clock
signal to the CLK_OUT pin of the J2 Output Header. If
jumpers are inserted as shown in Figure 6, the CLK_OUT
pin of the J2 Output Connector drives the clock buffer which
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