HI3026 Datasheet, PDF (9/17 Pages) Intersil Corporation – 8-Bit, 120 MSPS, Flash A/D Converter

HI3026
TABLE 1. A/D CODE TABLE
V_IN
V_RT
V_RM2
V_RB
INV
1
0
STEP D7
D0 D7
D0
255 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
254 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1
•
•
•
•
•
•
•
•
•
128 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
127 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
•
•
•
•
•
•
•
•
•
1 0000000111111110
0 0000000011111111
Notes on Operation
• The HI3026 is a high-speed A/D converter which is capable
of TTL, ECL and PECL level clock input. Characteristic
impedance should be properly matched to ensure optimum
performance during high-speed operation.
• The power supply and grounding have a profound influence
on converter performance. The power supply and ground-
ing method are particularly important during high-speed
operation. General points for caution are as follows:
- The ground pattern should be as large as possible. It is
recommended to make the power supply and ground
patterns wider at an inner layer using a multi-layer
board.
- To prevent interference between AGND and DGND and
between AV_CC and DV_CC, make sure the respective pat-
terns are separated. To prevent a DC offset in the power
supply pattern, connect the AV_CC and DV_CC lines at one
point each, via a ferrite-bead filter. Shorting the AGND
and DGND patterns in one place immediately under the
A/D converter improves A/D converter performance.
- Ground the power supply pins (AV_CC, DV_CC1, DV_CC2,
DV_EE3) as close to each pin as possible with a 0.1µF or
larger ceramic chip capacitor. (Connect the AV_CC pin to
the AGND pattern and the DV_CC1, DV_CC2, DV_EE3 pins
to the DGND pattern).
- The digital output wiring should be as short as possible.
If the digital output wiring is long, the wiring capacitance
will increase, deteriorating the output slew rate and
resulting in reflection to the output waveform since the
original output slew rate is quite fast.
• The analog input pin V_IN has an input capacitance of
approximately 21pF. To drive the A/D converter with
proper frequency response, it is necessary to prevent per-
formance deterioration due to parasitic capacitance or
parasitic inductance by using a large capacity drive circuit;
keeping wiring as short as possible, and using chip parts
for resistors and capacitors, etc.
• The V_RT and V_RB pins must have adequate bypass to pro-
tect them from high-frequency noise. Bypass them to
AGND with approximately 1µF tantal capacitor and, 0.1µF
capacitor. At this time, approximately DGND3 - 1.2V voltage
is generated. However, this is not recommended for use as
threshold voltage V_BB as it is too weak.
When the digital input level is ECL or PECL level, ***/E pins
should be used and ***/T pins left open. When the digital
input level is TTL, ***/T pins should be used and III/E pins
left open.
Test Circuits
4V
1.95V
2V
V_RT
V_IN
V_RB
5V
5V
A I_CC
AV_CC
DV_CC1
DV_CC2
A I_EE
DGND3
CLK/E
5MHz PECL
DGND2
DGND1
AGND
DV_EE3
FIGURE 4. CURRENT CONSUMPTION MEASUREMENT
CIRCUIT
+V
S2
-
+
S1 ^{S1: ON WHEN A < B}
S2: ON WHEN A > B
V_IN
DVM
HI3026
-V
A<B A>B
COMPARATOR
8
A8 B8
TO TO
8
BUFFER
A1 B1
A0 B0
“0”
“1”
CONTROLLER
000...00
TO
111..10
FIGURE 5. INTEGRAL LINEARITY ERROR/DIFFERENTIAL
LINEARITY ERROR MEASUREMENT CIRCUIT
4-1370