HI2303 Datasheet, PDF (9/18 Pages) Intersil Corporation – Triple 8-Bit, 50 MSPS, Video A/D Converter with Clamp Function

Test Circuits (Continued)
HI2303
NTSC
SIGNAL
SOURCE
AMP
40 IRE
MODULATION
100
BURST
0
-40 _SYNC
FC
S.G.
(CW)
A_IN
B_{IN DUT}
C_IN ^HI2303
2.5V
0.5V
A8
8
B
8
C
HI20201
8
TTL
↓
8
ECL
10-BIT
D/A
620
CLK
-5.2V
VECTOR
SCOPE
D.G.
D.P.
TTL
↓
ECL
620
-5.2V
FIGURE 5. DIFFERENTIAL GAIN AND PHASE ERROR vs TEST CIRCUIT
2.5V
0.5V
V_DD
A_RT, B_AT, C_RT
A_IN, B_IN, C_IN
DATA
A_RB, B_RB, C_{RB OUT}
CLK
OE
V_SS
I_OL
A
+
V_{OL -}
2.5V
0.5V
V_DD
A_RT, B_RT, C_RT
A_IN, B_IN, C_IN
DATA
A_RB, B_RB, C_{AB OUT}
CLK
OE
V_SS
I_OL
A
+
V_OL
-
FIGURE 6. DIGITAL OUTPUT TEST CIRCUIT
Description of Operation
Digital Output Format
The HI2303 supports eight different output formats as
detailed in Table 2. For clarity, these formats are labeled
mode 0 to 7. The modes are selected via three control pins
labeled CTL0, CTL1 and CTL2.
The converter has a latency of five clock cycles which places
a constraint on the users ability to change the mode on the
fly without corrupting the data within the converter. Please
refer to Figure 10. The SY pin is used to control mode
changes. This is achieved by using the SY as a reset/latch
signal. The Mode is reset when the SY is asserted low.
When SY transitions from low to high the control pins are
latched internally and mode is changed per timing diagram
latency.
TABLE 2. SETTING VALUES AND OUTPUT FORMATS
SETTING
OUTPUT
CTL2 CTL1 CTLO MODE
FORMAT
L
L
L
0 4:4:4
L
L
H
L
H
L
1 4:2:2 (8F_S)
2 4:2:2 (D2)
L
H
H
3 4:2:2 (Special)
H
L
L
4 4:1:1
H
L
H
5 4:1:1 (Special)
H
H
L
6 Simple Boundary, Scan 1
H
H
H
7 Simple Boundary, Scan 2
9