HA5024_06 Datasheet, PDF (9/16 Pages) Intersil Corporation – Quad 125MHz Video Current Feedback Amplifier with Disable

HA5024
Referring to Figure 10, both inputs are terminated in their
characteristic impedance; 75Ω is typical for video
applications. Since the drivers usually are terminated in their
characteristic impedance the input gain is 0.5, thus the
amplifiers, U₂, are configured in a gain of +2 to set the circuit
gain equal to one. Resistors R₂ and R₃ determine the amplifier
gain, and if a different gain is desired R₂ should be changed
according to the equation G = (1 + R₃/R₂). R₃ sets the
frequency response of the amplifier so you should refer to the
manufacturers data sheet before changing its value. R₅, C₁
and D₁ are an asymmetrical charge/discharge time circuit
which configures U₁ as a break before make switch to prevent
both amplifiers from being active simultaneously. If this design
is extended to more channels the drive logic must be designed
to be break before make. R₄ is enclosed in the feedback
loop of the amplifier so that the large open loop amplifier
gain of U₂ will present the load with a small closed loop
output impedance while keeping the amplifier stable for all
values of load capacitance.
The circuit shown in Figure 10 was tested for the full range of
capacitor values with no oscillations being observed; thus,
problem one has been solved.The frequency and gain
characteristics of the circuit are now those of the amplifier
independent of any multiplexing action; thus, problem two
has been solved. The multiplexer transition time is
approximately 15µs with the component values shown.
INPUT B
INPUT A
CHANNEL
SWITCH
INHIBIT
R_1B
75
U_1A
R₆
100K
R_1A
75
D_1A
1N4148
U_1C
R_5A
2000
C_1A
0.047µF
U_1B
U_1D
R_3A
681
R_1A
681
100Ω
U_2A
1
-
+
16
4
23
R_4A
27
-5V
(NOTE 17)
0.01µF
R_3B
681
R_5B
2000
R_2B
681
7 ^U2B
- ¹⁰
R_4B
27
6 ⁺ ₁₃
100Ω
5
+5V
(NOTE 17)
0.01µF
OUTPUT
D_1B
1N4148
C_1B
0.047µF
NOTES:
22. U₂: HA5022/24.
23. U₁: CD4011.
FIGURE 10. LOW IMPEDANCE MULTIPLEXER
9
3550.6
February 8, 2006