CD4518BMS Datasheet, PDF (9/10 Pages) Intersil Corporation – CMOS Dual Up Counters

CD4518BMS, CD4520BMS
CLOCK
INPUT
VDD
1
2
7
CLOCK ENABLE RESET
A
A
A
9
10
15
CLOCK ENABLE RESET
B
B
B
Q1A Q2A Q3A Q4A
3456
Q1B Q2B Q3B Q4B
11 12 13 14
CD4518BMS/20BMS
1
2
7
CLOCK ENABLE RESET
A
A
A
9
10
15
CLOCK ENABLE RESET
B
B
B
Q1A Q2A Q3A Q4A
3456
Q1B Q2B Q3B Q4B
11 12 13 14
CD4518BMS/20BMS
FIGURE 13. RIPPLE CASCADING OF FOUR COUNTERS WITH POSITIVE EDGE TRIGGERING
CLOCK*
INPUT
CD4071
CD4071
1
2
3
CLOCK ENABLE RESET
A
A
A
9
10
15
CLOCK ENABLE RESET
B
B
B
Q1A Q2A Q3A Q4A
3456
CD4520BMS
CD4012A
Q1B Q2B Q3B Q4B
11 12 13 14
CD4012A
1
2
3
CLOCK ENABLE RESET
A
A
A
9
10
15
CLOCK ENABLE RESET
B
B
B
Q1A Q2A Q3A Q4A
3456
CD4520BMS
CD4012A
Q1B Q2B Q3B Q4B
11 12 13 14
CD4520BMS
* For synchronous cascading, the clock transition time should be made less than or equal to the sum of the fixed propagation delay at 15pF
and the transition time of the output driver stage for the estimated capacitive load.
FIGURE 14. SYNCHRONOUS CASCADING OF FOUR BINARY COUNTERS WITH NEGATIVE EDGE TRIGGERING
7-1214