82C84A_05 Datasheet, PDF (9/11 Pages) Intersil Corporation – CMOS Clock Generator Driver

82C84A
Test Load Circuits
OUTPUT FROM
DEVICE UNDER TEST
2.25V
R = 740Ω FOR ALL OUTPUTS
EXCEPT CLK
463Ω FOR CLK OUTPUT
C_L
(SEE NOTE 3)
NOTES:
1. C_L =100pF for CLK output.
2. C_L = 50pF for all outputs except CLK.
3. C_L = Includes probe and jig capacitance.
FIGURE 5. TEST LOAD MEASUREMENT CONDITIONS
X1
CLK
LOAD
PULSE
EF1
CLK
LOAD
(SEE NOTE 1)
GENERATOR
(SEE NOTE 1)
C1
X2
V_CC
C2
F/C
F/C
CSYNC
CSYNC
FIGURE 6. TCHCL, TCLCH LOAD CIRCUITS
24MHz
PULSE
GENERATOR
TRIGGER
V_CC
C1
C2
AEN1 CLK
X1
READY
X2
RDY2 OSC
F/C
AEN2
CSYNC
LOAD
(SEE NOTE 1)
LOAD
(SEE NOTE 2)
PULSE
GENERATOR
TRIGGER
PULSE
GENERATOR
V_CC
EF1
CLK
F/C
AEN1
RDY2 ^READY
AEN2
CSYNC
LOAD
(SEE NOTE 1)
LOAD
(SEE NOTE 2)
FIGURE 7. TRYLCL, TRYHCH LOAD CIRCUITS
AC Testing Input, Output Waveform
INPUT
V_IH + 0.4V
OUTPUT
V_OH
1.5V
1.5V
V_IL - 0.4V
V_OL
NOTE: Input test signals must switch between V_IL (maximum) -0.4V and V_IH (minimum) +0.4V. RES and F/C must switch between 0.4V
and V_CC -0.4V. Input rise and fall times driven at 1ns/V. V_IL ≤ V_IL (max) -0.4V for CSYNC pin. V_CC -4.5V and 5.5V.
9
FN2974.3
December 6, 2005