ISL98012 Datasheet, PDF (8/10 Pages) Intersil Corporation – 1.8V Input PWM Step-Up Regulator

ISL98012
completely dried out before the MOSFET is turned on again.
The input voltage source, the inductor, and the MOSFET and
output diode parasitic capacitors form a resonant circuit.
Oscillation will occur in this period. This oscillation is normal
and will not affect regulation.
At very low load, the MOSFET will skip pulses sometimes;
this is normal.
Current Limit
The MOSFET current limit is nominally 1.4A and guaranteed
1A. This restricts the maximum output current I_OMAX based
on Equation 1:
I_OMAX
=
⎛
⎝
1
–
Δ_---2--I_{--L-⎠⎞}
×
V_-----I--N--
V_O
(EQ. 1)
where:
• ΔI_L is the inductor peak-to-peak current ripple and is
decided by Equation 2:
ΔI_L
=
-^V----^I--^N--
L
×
-^D---
f_S
(EQ. 2)
• D is the MOSFET turn-on ratio and is decided by
Equation 3:
D
=
-^V----^O-----–-----^V----^I--^N--
V_O
(EQ. 3)
• f_S is the switching frequency
Table1 gives typical values:
TABLE 1. MAX CONTINUOUS OUTPUT CURRENTS
V_IN
V_O
L
f_S
I_OMAX
(V)
(V)
(µH)
(kHz)
(mA)
2
5
10
750
360
2
9
10
750
190
2
12
10
750
140
3.3
5
10
750
600
3.3
9
10
750
310
3.3
12
10
750
230
5
9
10
750
470
5
12
10
750
340
9
12
10
750
630
12
15
10
750
670
Component Considerations
It is recommended that C_IN is larger than 10µF.
Theoretically, the input capacitor has a ripple current of ΔI_L.
Due to high-frequency noise in the circuit, the input current
ripple may exceed the theoretical value. A larger capacitor
will reduce the ripple further.
The inductor has peak and average current decided by
Equations 4 and 5:
I_LPK
=
I_L
A
V
G
+
-^Δ----^I--^L-
2
(EQ. 4)
I_LAVG
=
----^I--^O-------
1–D
(EQ. 5)
The inductor should be chosen to handle this current.
Furthermore, due to fixed internal compensation, it is
recommended that maximum inductance of 10µH and 15µH
be used in the 5V and 12V or higher output voltage,
respectively.
The output diode has an average current of I_O and peak
current is the same as the inductor's peak current. A
Schottky diode is recommended and it should be able to
handle those currents.
The output voltage ripple can be calculated as Equation 6:
ΔV_O
=
---^I--^O------^×-----^D-----
F_S × C_O
+
I_LPK
×
ESR
(EQ. 6)
Where:
• C_O is the output capacitance.
• The ESR is the output capacitor ESR value.
Low ESR capacitors should be used to minimize output
voltage ripple. Multilayer ceramic capacitors (X5R and X7R)
are preferred for output capacitors since they have a low
ESR and small packages. Tantalum capacitors also can be
used, but they take more board space and have higher ESR.
A minimum of 22µF output capacitor is sufficient for high
output current application. For lower output current, the
output capacitor can be smaller, like 4.7µF. The capacitor
should always have enough voltage rating. In addition to the
voltage rating, the output capacitor should also be able to
handle the RMS current, which is given by Equation 7:
I_CORMS =
(1
–
D)
×
⎛
⎜⎜^D
⎝
+
-----^Δ----^I--^L---²-----
I_L
A
V
2
G
×
1^--1--2^{--⎟⎟⎞}
⎠
×
I_LAVG
(EQ. 7)
Output Voltage
An external resistor divider is required to divide the output
voltage down to the nominal reference voltage. The current
drawn by the resistor network should be limited to maintain
the overall converter efficiency. The maximum value of the
resistor network is limited by the feedback input bias current
and the potential for noise being coupled into the feedback
pin. A resistor network less than 300kΩ is recommended.
8
FN6654.0
October 15, 2008