ISL97536 Datasheet, PDF (8/9 Pages) Intersil Corporation – Monolithic 1A Step-Down Regulator with Low Quiescent Current

ISL97536
Component Selection
Because of the fixed internal compensation, the component
choice is relatively narrow. For a regulator with fixed output
voltage, only two capacitors and one inductor are required.
Capacitors must be chosen in the range of 10µF to 40µF,
multilayer ceramic capacitors with X5R or X7R rating for
both the input and output capacitors, and inductors in the
range of 1.5µH to 2.2µH.
The RMS current present at the input capacitor is decided by
the following formula:
I_INRMS
=
-----^V----^O------^×----⁽---^V----^I--^N-----–-----^V----^O----⁾-
V_IN
×
I_O
(EQ. 3)
This is about half of the output current I_O for all the V_O. This
input capacitor must be able to handle this current.
The inductor peak-to-peak ripple current is given as:
∆I_IL
=
(_---V_{----I--N------–----}V_-----O----)_----×_-----V_----O--
L × V_IN × f_S
(EQ. 4)
L is the inductance
f_S the switching frequency (nominally 1.4MHz)
The inductor must be able to handle I_O for the RMS load
current, and to assure that the inductor is reliable, it must
handle the 2A surge current that can occur during a current
limit condition.
In addition to decoupling capacitors and inductor value, it is
important to properly size the phase-lead capacitor C₄
(Refer to the Typical Application Diagram). The phase-lead
capacitor creates additional phase margin in the control loop
by generating a zero and a pole in the transfer function. As a
general rule of thumb, C₄ should be sized to start the phase-
lead at a frequency of ~2.5kHz. The zero will always appear
at lower frequency than the pole and follow the equation
below:
f_Z
=
----------¹------------
2πR₂C₄
(EQ. 5)
Over a normal range of R₂ (~10-100k), C₄ will range from
~470-4700pF. The pole frequency cannot be set once the
zero frequency is chosen as it is dictated by the ratio of R₁
and R₂, which is solely determined by the desired output set
point. The equation below shows the pole frequency
relationship:
f_P
=
-------------------¹--------------------
2π(R₁ R₂)C₄
(EQ. 6)
Layout Considerations
The layout is very important for the converter to function
properly. The following PC layout guidelines should be
followed:
1. Separate the Power Ground ( ) and Signal Ground
( ); connect them only at one point right at the pins
2. Place the input capacitor as close to V_IN and PGND pins
as possible
3. Make the following PC traces as small as possible:
- from LX pin to L
- from C_O to PGND
4. If used, connect the trace from the FB pin to R₁ and R₂
as close as possible
5. Maximize the copper area around the PGND pin
6. Place several via holes under the chip to additional
ground plane to improve heat dissipation
The demo board is a good example of layout based on this
outline. Please refer to the ISL97536 Application Brief.
8
FN6279.0
October 5, 2006