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| ISL6548_06 Datasheet, PDF (8/15 Pages) Intersil Corporation – ACPI Regulator/Controller for Dual Channel DDR Memory Systems | |||
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SLP_S3#
SLP_S5#
12V
POR
12V
0V
VDDQ_DDR
0V
VDDQ_DDR
VTT_DDR
0V
VTT_DDR Soft-Start Rise Time Dependent Upon Capacitor On VREF_IN Pin
VTT_DDR FLOATING
VGMCH_UPPER
0V
VGMCH
0V
VTT_GMCH/CPU
0V
VIDPGD
(3 SOFTSTART CYCLES)
t0
t1
t2
t3
t4
t5
t6
t7
(3 SOFTSTART CYCLES)
t8
t9
t10 t11 t12 t13 t14
t15
FIGURE 1. ISL6548 TIMING DIAGRAM
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