ISL6528_06 Datasheet, PDF (8/13 Pages) Intersil Corporation – Dual Regulator - Standard Buck PWM and Linear Power Controller

ISL6528
Compensation Break Frequency Equations
Poles:
F_P1
=
---------------------------1----------------------------
2
π
×
R₂
×


C-C----11-----+^{×-----CC-----22--}
F_P2 = _2----π-----_×-----R---1--3-----_×----C-----3--
Zeros:
F_Z1 = _2----π-----_×-----R---1--2-----_×----C-----1--
(EQ. 8)
(EQ. 9)
(EQ. 10)
F_Z2
=
---------------------------1---------------------------
2π × (R1 + R3) × C3
(EQ. 11)
Follow this procedure for selecting compensation
components by locating the poles and zeros of the
compensation network:
1. Set the loop gain (R2/R1) to provide a converter
bandwidth of one quarter of the switching frequency.
2. Place the first compensation zero, F_Z1, below the output
filter double pole (~75% F_LC).
3. Position the second compensation zero, F_Z2, at the
output filter double pole, F_LC.
4. Locate the first compensation pole, F_P1, at the output filter
ESR zero, F_ESR.
5. Position the second compensation pole at half the
converter switching frequency, F_SW.
6. Check gain against error amplifier’s open-loop gain.
7. Estimate phase margin; repeat if necessary.
8.
F_Z1
F_Z2 F_P1 F_P2
OPEN LOOP
100
ERROR AMP GAIN
80
20
log



V----V-O---I--S-N---C---_{}
60
40
COMPENSATION
GAIN
20
0
-20
20log


-^RR-----²₁--_
MODULATOR
-40
GAIN
F_LC F_ESR
LOOP GAIN
-60
10
100
1K
10K 100K 1M 10M
FREQUENCY (Hz)
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Figure 6 shows an asymptotic plot of the DC/DC converter’s
gain vs. frequency. The actual modulator gain has a high
gain peak dependent on the quality factor (Q) of the output
filter, which is not shown in Figure 6. Using the above
procedure should yield a compensation gain similar to the
curve plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at F_P2
with the capabilities of the error amplifier.
The compensation gain uses external impedance networks
Z_FB and Z_IN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin.
Application Guidelines
Layout Considerations
Layout is very important in high frequency switching
converter design. With power devices switching efficiently at
600kHz, the resulting current transitions from one device to
another cause voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage
spikes can degrade efficiency, radiate noise into the circuit,
and lead to device overvoltage stress. Careful component
layout and printed circuit board design minimizes the voltage
spikes in the converters.
As an example, consider the turn-off transition of the PWM
MOSFET. Prior to turn-off, the MOSFET is carrying the full
load current. During turn-off, current stops flowing in the
MOSFET and is picked up by the lower Schottky diode. Any
parasitic inductance in the switched current path generates a
large voltage spike during the switching interval. Careful
component selection, tight layout of the critical components,
and short, wide traces minimizes the magnitude of voltage
spikes.
There are two sets of critical components in a DC/DC
converter using the ISL6528. The switching components are
the most critical because they switch large amounts of
energy, and therefore tend to generate large amounts of
noise. Next are the small signal components which connect
to sensitive nodes or supply critical bypass current and
signal coupling.
A multi-layer printed circuit board is recommended. Figure 7
shows the connections of the critical components in the
converter. Note that capacitors C_IN and C_OUT could each
represent numerous physical capacitors. Dedicate one solid
layer, usually a middle layer of the PC board, for a ground
plane and make all critical component ground connections
through vias to this layer. Dedicate another solid layer as a
power plane and break this plane into smaller islands of
common voltage levels. Keep the metal runs from the
PHASE terminal to the output inductor short. The power
plane should support the input and output power nodes. Use
copper filled polygons on the top and bottom circuit layers for
the phase node. Use the remaining printed circuit layers for
small signal wiring. The wiring traces from the UGATE pin to
the MOSFET gate should be kept short and wide enough to
easily handle the 1A of drive current.
The switching components should be placed close to the
ISL6528 first. Minimize the length of the connections
between the input capacitors, C_IN, and the power switches
8
FN9038.4
March 9, 2006