ISL6520ACB-T Datasheet, PDF (8/12 Pages) Intersil Corporation – Single Synchronous Buck Pulse-Width Modulation (PWM) Controller

ISL6520A
4. Place 1^ST Pole at the ESR Zero.
5. Place 2^ND Pole at Half the Switching Frequency.
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
Compensation Break Frequency Equations
F_Z1
=
-----------------1------------------
2π x R₂ x C₁
F_Z2
=
---------------------------1---------------------------
2π x (R₁ + R₃) x C₃
F_P1
=
---------------------------1-----------------------------
2π
x
R₂
x
⎛
⎜
⎝
C-C----_{11-----+x-----CC----2-2-⎠⎟⎞}
F_P2
=
-----------------1------------------
2π x R₃ x C₃
(EQ. 5)
Figure 6 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 6. Using the previously mentioned guidelines
should give a Compensation Gain similar to the curve plotted.
The open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at F_P2 with the
capabilities of the error amplifier. The Closed Loop Gain is
constructed on the graph of Figure 6 by adding the Modulator
Gain (in dB) to the Compensation Gain (in dB). This is
equivalent to multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
The compensation gain uses external impedance networks
Z_FB and Z_IN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
100
F_Z1 F_Z2 F_P1 F_P2
80
OPEN LOOP
60
ERROR AMP GAIN
40
20LOG
20 ^(R2^/R1⁾
0
MODULATOR
-20
GAIN
20LOG
(V_IN/DV_OSC)
COMPENSATION
GAIN
CLOSED LOOP
-40
GAIN
F_LC
F_ESR
-60
10
100
1K
10K 100K 1M 10M
FREQUENCY (Hz)
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern components and loads are capable of producing
transient load rates above 1A/ns. High frequency capacitors
initially supply the transient and slow the current load rate
seen by the bulk capacitors. The bulk filter capacitor values
are generally determined by the ESR (Effective Series
Resistance) and voltage rating requirements rather than
actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor’s ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the Equivalent Series Inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by the following equations:
ΔI = ^{VIN - VOUT} _x ^VOUT
Fs x L
V_IN
ΔV_OUT = ΔI x ESR
(EQ. 6)
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
One of the parameters limiting the converter’s response to
a load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6520A will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
8
FN9016.6
December 10, 2009