ISL6431 Datasheet, PDF (8/10 Pages) Intersil Corporation – Advanced Pulse-Width Modulation (PWM) Controller for Home Gateways

ISL6431
The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:
t_RISE =
L x I_TRAN
V_IN - V_OUT
t_FALL =
L x I_TRAN
V_OUT
where: I_TRAN is the transient load current step, t_RISE is the
response time to the application of load, and t_FALL is the
response time to the removal of load. The worst case
response time can be either at the application or removal of
load. Be sure to check both of these equations at the
minimum and maximum output levels for the worst case
response time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time Q₁ turns on. Place the
small ceramic capacitors physically close to the MOSFETs
and between the drain of Q₁ and the source of Q₂.
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 the DC load current.
For a through hole design, several electrolytic capacitors may
be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These capacitors
must be capable of handling the surge-current at power-up.
Some capacitor series available from reputable manufacturers
are surge current tested.
MOSFET Selection/Considerations
The ISL6431 requires two N-Channel power MOSFETs for use
in a synchronous buck configuration. These should be selected
based upon r_DS(ON), gate supply requirements, and thermal
management requirements.
In high-current applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The power dissipation includes
two loss components; conduction loss and switching loss.
The conduction losses are the largest component of power
dissipation for both the upper and the lower MOSFETs.
These losses are distributed between the two MOSFETs
according to duty factor (see the equations below). Only
the upper MOSFET has switching losses, since the lower
MOSFETs body diode or an external Schottky rectifier
across the lower MOSFET clamps the switching node
before the synchronous rectifier turns on. These equations
assume linear voltage-current transitions and do not
adequately model power loss due the reverse-recovery of
the lower MOSFET’s body diode. The gate-charge losses
are dissipated by the ISL6431 and don't heat the
MOSFETs. However, large gate-charge increases the
switching interval, t_SW which increases the upper MOSFET
switching losses. Ensure that both MOSFETs are within
their maximum junction temperature at high ambient
temperature by calculating the temperature rise according
to package thermal-resistance specifications. A separate
heatsink may be necessary depending upon MOSFET
power, package type, ambient temperature and air flow.
P_UPPER = Io² x r_DS(ON) x D +
1
2
Io x V_IN x t_SW x F_S
P_LOWER = Io² x r_DS(ON) x (1 - D)
Where: D is the duty cycle = V_OUT / V_IN ,
t_SW is the switch ON time, and
F_S is the switching frequency.
Given the reduced available gate bias voltage (5V), logic-
level or sub-logic-level transistors have to be used for both
N-MOSFETs. Caution should be exercised with devices
exhibiting very low V_GS(ON) characteristics, as the low gate
threshold could be conducive to some shoot-through (due to
the Miller effect), in spite of the counteracting circuitry
present aboard the ISL6431.
+5V
D_BOOT
VCC
ISL6431
+ V_D -
+5V
BOOT
C_BOOT
Q1
UGATE
PHASE
Q2
-
LGATE
+
GND
NOTE:
V_G-S ≈ V_CC -V_D
NOTE:
V_G-S ≈ V_CC
FIGURE 7. UPPER GATE DRIVE BOOTSTRAP
Figure 7 shows the upper gate drive (BOOT pin) supplied by a
bootstrap circuit from V_CC. The boot capacitor, C_BOOT,
develops a floating supply voltage referenced to the PHASE
pin. The supply is refreshed to a voltage of V_CC less the boot
diode drop (V_D) each time the lower MOSFET, Q₂, turns on.
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