ISL6265A Datasheet, PDF (8/23 Pages) Intersil Corporation – Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable Mobile CPUs

ISL6265A
Electrical Specifications
VCC = PVCC = 5V, V_IN = 12V, T_A = -10°C to +100°C, Unless Otherwise Specified. Parameters with MIN and/or
MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
OFFSET FUNCTION
OFS Pin Voltage For Droop Enabling
FB Pin Source Current
OFS Pin Voltage Threshold for VFIX
Mode and No Droop Operation
V_OFS
I_FB
V_OFS
R_OFS = 240kΩ (OFS pin to GND)
I_OFS = 10µA
1.18 1.2 1.22 V
9.0 9.9 10.8 µA
-
1.8
-
V
OFS Pin Voltage Threshold for SVI
Mode and No Droop Operation
V_OFS
-
4.0
-
V
OFS Bias
LOGIC INPUTS
I_OFS
1.8V < OFS < VCC
-
4.0
-
µA
ENABLE Low Threshold
ENABLE High Threshold
ENABLE Leakage Current
V_IL(3.3V)
V_IH(3.3V)
Logic input is low
- 1.35 0.9
V
2.0 1.6
-
V
-1
0
-
µA
Logic input is high at 3.3V
-
0
1
µA
SVI INTERFACE
PWROK Input Low Threshold
- 0.65 0.8
V
PWROK Input High Threshold
-
0.9
-
V
SVC, SVD Input HIGH (VIH)
1.05 0.87 -
V
SVC, SVD Input LOW (VIL)
- 0.68 0.45 V
Schmitt Trigger Input Hysteresis
- 0.19 -
V
SVD Low Level Output Voltage
3mA Sink Current
-
0.1 0.285 V
SVC, SVD Leakage
EN = 0V, SVC, SVD = 0V
- < -100 -
nA
EN = 5V, SVC, SVD = 1.8V
- < -100 -
nA
DIFF AMP
Accuracy
VSEN = 0.5V to 1.55V; RTN = 0 ±0.1V
-2
-
2
mV
NOTES:
3. Limits should be considered typical and are not production tested.
4. Limits established by characterization and are not production tested.
ISL6265A Gate Driver Timing Diagram
PWM
UGATE
t_PDHU
t_RU
LGATE
1V
t_FL
t_FU
1V
t_RL
t_PDHL
8
FN6884.0
May 11, 2009