ISL12059 Datasheet, PDF (8/11 Pages) Intersil Corporation – Low Cost and Low Power I2C Bus™ Real Time Clock/Calendar

ISL12059
LEAP YEARS
Leap years add the day February 29 and are defined as those
years that are divisible by 4. Years divisible by 100 are not leap
years, unless they are also divisible by 400. This means that
the year 2000 is a leap year, the year 2100 is not. The
ISL12059 does not correct for the leap year in the year 2100.
Control and Status Register
FT/OUT Control Register (FT/OUT) [Address 07h]
TABLE 2. FT/OUT CONTROL REGISTER
ADDR 7
6
543210
07h
OUT
FT
0 0 0 0 0 PF
Default 1
0
000001
POWER FAILURE BIT (PF)
This bit is set to a “1” after a total power failure. This is a read
only bit that is set by hardware (ISL12059 internally) when
the device powers up after having lost power to the device.
On power-up after a total power failure, all registers are set
to their default states. The first valid write to the RTC section
after a complete power failure resets the PF bit to “0” (writing
one byte is sufficient).
512HZ FREQUENCY OUTPUT ENABLE BIT (FT)
This bit enables/disables the 512Hz frequency output on the
FT/OUT pin. When the FT is set to “1”, the FT/OUT pin
outputs the 512Hz frequency, regardless of the Digital Output
selection bit (OUT). When the FT is set to “0”, the 512Hz
frequency is disabled and the function of FT/OUT pin is
selected by the Digital Output selection bit (OUT). The FT bit
is set to “0” on power-up.
DIGITAL OUTPUT SELECTION BIT (OUT)
This bit selects the output status of the FT/OUT. 512Hz
Frequency Output Enable bit (FT) must be set to “0”
(disable) for OUT to take effect on FT/OUT pin. When the
OUT is set to “1”, and FT is set to “0”, the FT/OUT is set to
logic level high. The FT/OUT voltage level is controlled by
the voltage of the pull-up resistor on FT/OUT pin. When the
OUT is set to “0”, and FT is set to “0”, the FT/OUT is set to
logic level low. The voltage level of FT/OUT is set to VOL
level. The OUT bit is set to “1” on power-up.
I²C Serial Interface
The ISL12059 supports a bi-directional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is the master
and the device being controlled is the slave. The master
always initiates data transfers and provides the clock for
both transmit and receive operations. Therefore, the
ISL12059 operates as a slave device in all applications.
All communication over the I²C bus is conducted by sending
the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (see
Figure 5). On power-up of the ISL12059, the SDA pin is in
the input mode.
All I²C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL12059 continuously monitors the SDA
and SCL lines for the START condition and does not respond
to any command until this condition is met (see Figure 5). A
START condition is ignored during the power-up sequence.
All I²C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (see Figure 5). A STOP condition at the end of
a read operation or at the end of a write operation to memory
only places the device in its standby mode.
An acknowledge (ACK) is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting 8 bits. During the ninth clock cycle, the receiver
pulls the SDA line LOW to acknowledge the reception of the
8 bits of data (see Figure 6).
The ISL12059 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL12059 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
SCL
SDA
START
DATA
DATA
DATA
STABLE CHANGE STABLE
STOP
FIGURE 5. VALID DATA CHANGES, START, AND STOP CONDITIONS
8
FN6757.0
June 15, 2009