ICL8052A Datasheet, PDF (8/23 Pages) Intersil Corporation – Precision 4 1/2 Digit, A/D Converter

ICL8052A/ICL71C03, ICL8068A/ICL71C03
4¹/₂ DIGIT
3¹/₂ DIGIT
COUNTS
PHASE I
PHASE II
10,001
10,000
1,001
1,000
PHASE III
20,001
2,001
INTEGRATOR
OUTPUT
CLOCK
AZ PHASE I
POLARITY
DETECTED
INT PHASE II
ZERO CROSSING
OCCURS
ZERO CROSSING
DETECTED
DEINT PHASE III
AZ
INTERNAL LATCH
BUSY OUTPUT
NUMBER OF COUNTS TO ZERO CROSSING
PROPORTIONAL TO V_IN
FIGURE 3. CONVERSION TIMING
AFTER ZERO CROSSING,
ANALOG SECTION WILL
BE IN AUTOZERO
CONFIGURATION
Zero-Crossing Flip-Flop
Figure 4 shows the problem that the zero-crossing F/F is
designated to solve.
The integrator output is approaching the zero-crossing point
where the count will be latched and the reading displayed.
For a 20,000 count instrument, the ramp is changing
approximately 0.50mV per clock pulse (10V Max integrator
output divided by 20,000 counts). The clock pulse
feedthrough superimposed upon this ramp would have to be
less than 100mV peak to avoid causing significant errors.
The flip-flop interrogates the data once every clock pulse
after the transients of the previous clock pulse and half-clock
pulse have died down. False zero-crossings caused by clock
pulses are not recognized. Of course, the flip-flop delays the
true zero-crossing by one count in every instance, and if a
correction were not made, the display would always be one
count too high. Therefore, the counter is disabled for one
clock pulse at the beginning of phase 3. This one count
delay compensates for the delay of the zero crossing flip-
flop, and allows the correct number to be latched into the
display. Similarly, a one count delay at the beginning of
phase 1 gives an overload display of 0000 instead of 0001.
No delay occurs during phase 2, so that true ratiometric
readings result.
CLOCK
PULSE
FEEDTHROUGH
FALSE ZERO
CROSSING
TRUE ZERO
CROSSING
FIGURE 4. INTEGRATOR OUTPUT NEAR ZERO-CROSSING
Detailed Description
Digital Section
The 71C03 includes several pins which allow it to operate
conveniently in more sophisticated systems. These include:
4-1/2 / 3-1/2 (PIN 2)
When high (or open) the internal counter operates as a full
4¹/₂ decade counter, with a complete measurement cycle
requiring 40,002 counts. When held low, the least significant
decade is cleared and the clock is fed directly into the next
decade. A measurement cycle now requires only 4,0002
clock pulses. All 5 digit drivers are active in either case, with
each digit lasting 200 counts with Pin 2 high (4¹/₂ digit) and
20 counts for Pin 2 low (3¹/₂ digit).
8