ICL7660S Datasheet, PDF (8/9 Pages) Intersil Corporation – Super Voltage Converter

ICL7660S
V+
C₁
+
-
1
8
2 _ICL7660S 7
3
6
4
5
C_OSC
-
V_OUT
+ ^C2
FIGURE 16. LOWERING OSCILLATOR FREQUENCY
Positive Voltage Doubling
The ICL7660S may be employed to achieve positive voltage
doubling using the circuit shown in Figure 20. In this
application, the pump inverter switches of the ICL7660S are
used to charge C₁ to a voltage level of V+ -V_F (where V+ is
the supply voltage and V_F is the forward voltage on C₁ plus
the supply voltage (V+) is applied through diode D₂ to
capacitor C₂. The voltage thus created on C₂ becomes
(2V+) - (2V_F) or twice the supply voltage minus the
combined forward voltage drops of diodes D₁ and D₂.
The source impedance of the output (V_OUT) will depend on
the output current, but for V+ = 5V and an output current of
10mA it will be approximately 60Ω.
V+
1
8
2 _ICL7660S 7
3
6
4
5
D₁
D₂
+
- ^C1
V_OUT =
(2V+) - (2V_F)
+
- ^C2
NOTE: D₁ and D₂ can be any suitable diode.
FIGURE 17. POSITIVE VOLTAGE DOUBLER
Combined Negative Voltage Conversion and
Positive Supply Doubling
Figure 21 combines the functions shown in Figure 14 and
Figure 20 to provide negative voltage conversion and
positive voltage doubling simultaneously. This approach
would be, for example, suitable for generating +9V and -5V
from an existing +5V supply. In this instance capacitors C₁
and C₃ perform the pump and reservoir functions
respectively for the generation of the negative voltage, while
capacitors C2 and C₄ are pump and reservoir respectively
for the doubled positive voltage. There is a penalty in this
configuration which combines both functions, however, in
that the source impedances of the generated supplies will be
somewhat higher due to the finite impedance of the common
charge pump driver at pin 2 of the device.
+
C₁
-
V+
1
8
2 _ICL7660S 7
D₁
3
6
4
5
-+
D₂
C₂
V_OUT = -V_IN
-
C₃
+
V_OUT = (2V+) -
(V_FD1) - (V_FD2)
+
- ^C4
FIGURE 18. COMBINED NEGATIVE VOLTAGE CONVERTER
AND POSITIVE DOUBLER
Voltage Splitting
The bidirectional characteristics can also be used to split a
high supply in half, as shown in Figure 22. The combined
load will be evenly shared between the two sides, and a high
value resistor to the LV pin ensures start-up. Because the
switches share the load in parallel, the output impedance is
much lower than in the standard circuits, and higher currents
can be drawn from the device. By using this circuit, and then
the circuit of Figure 17, +15V can be converted (via +7.5,
and -7.5 to a nominal -15V, although with rather high series
output resistance (∼250Ω).
V+
+
R_L1
50µF _-
1
8
V_OUT
=
V+
-
2
V-
+
50µF _-
2 _ICL7660S 7
3
6
R_L2
4
5
+
50µF _-
V-
FIGURE 19. SPLITTING A SUPPLY IN HALF
Regulated Negative Voltage Supply
In Some cases, the output impedance of the ICL7660S can
be a problem, particularly if the load current varies
substantially. The circuit of Figure 23 can be used to
overcome this by controlling the input voltage, via an
ICL7611 low-power CMOS op amp, in such a way as to
maintain a nearly constant output voltage. Direct feedback is
inadvisable, since the ICL7660S’s output does not respond
instantaneously to change in input, but only after the
switching delay. The circuit shown supplies enough delay to
accommodate the ICL7660S, while maintaining adequate
feedback. An increase in pump and storage capacitors is
desirable, and the values shown provides an output
impedance of less than 5Ω to a load of 10mA.
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