HSP43168_07 Datasheet, PDF (8/25 Pages) Intersil Corporation – Dual FIR Filter

HSP43168
reversed or non-reversed sample order. The MUX/DEMUX
structure at the input to the Feedback Circuitry routes data
to the LIFOs or the delay stage depending on the selected
configuration. The MUX on the Feedback Circuitry Output
selects which storage element feeds the Reverse Shifting
Decimation Registers.
In applications requiring reversal of sample order, the FIR
cells are configured with data reversal enabled (see
Table 2, CW5, bit 4 = 0). In this mode, data is transferred
from the forward to the backward Shifting Registers
through a pingponged LIFO structure. While one LIFO is
being read into the backward shifting path, the other LIFO
is written with data samples. The MUX/DEMUX controls
which LIFO is being written, and the MUX on the Feedback
Circuitry output controls which LIFO is being read. A low on
TXFR and SHIFTEN, switches the LIFOs being read and
written, which causes the block of data to be read from the
structure in reversed in sample order (See Example 4 in
“Application Examples” on page 10).
The frequency with which TXFR is asserted determines size
of the data blocks in which sample order is reversed. For
example, if TXFR is asserted once every three CLKs, blocks
of 3 data samples with order reversed, would be fed into the
Backward Decimation Registers. NOTE: Altering the
frequency or phase of TXFR assertion once a filtering
operation has begun will invalidate the filtering result.
In applications which do not require sample order reversal,
the FIR cells must be configured with data reversal
disabled (see Table 2, CW5, bit 4 = 1). In addition, TXFR
must be asserted to ensure proper data flow. In this
configuration, data to the backward shifting decimation path
is routed though a delay stage instead of the pingpong
LIFOs. The number of registers in the delay stage is based
on the programmed decimation factor. NOTE: Data
reversal must be disabled and TXFR must be asserted
for filtering applications which do not use decimation.
The shifting of data through the Forward and Reverse
Decimation Registers is enabled by asserting the SHFTEN
input. When SHFTEN is high, data shifting is disabled, and
the data sample latched into the part on the previous clock is
the last input to the filter structure. The data sample at the
filter input when SHFTEN is asserted, will be the next data
sample into the forward decimation path.
When operating the FIR cells as two independent filters, FIR
A receives input data via INA0-9 and FIR B receives data
from either INA0-9 or INB0-9 depending on the application
(see Table 1).
When the FIR cells are configured as a single extended
length filter, the forward and reverse decimation paths of the
two FIR cells are cascaded. In this mode, data is transferred
from the forward decimation path to the reverse decimation
path by the Data Feedback Circuitry in FIR B. Thus, the
manner in which data is read into the reverse decimation
path is determined by FIR B's configuration. When the
decimation paths are cascaded, data is routed through the
fourth delay stage in FIR A's forward path to FIR B.
The configuration of the FIR cells as even or odd length filters
determines the point in the forward decimation path from
which data is multiplexed to the Data Feedback Circuitry. For
example, if the FIR cell is configured as an odd length filter,
data prior to the last register in the third forward decimation
stage is routed to the Feedback Circuitry. If the FIR cell is
configured as an even length filter, data output from the third
forward decimation stage is multiplexed to the Feedback
Circuitry. This is required to ensure proper data alignment with
symmetric filter coefficients (See “Application Examples” on
page 10).
ALUs
Data shifting through the forward and reverse decimation
paths feed the “a” and “b” inputs of the ALUs respectively.
The ALUs perform an “b+a” operation if the FIR cell is
configured for even symmetric coefficients or an “b-a”
operation if configured for odd symmetric coefficients.
Control Word 0, Bit 5 is used to set the ALU operation.
For applications in which a pre-add or subtract is not required,
the “a” or “b” input can be zeroed by disabling FWRD or
RVRS respectively. This has the effect of producing an ALU
output which is either “a”, “-a”, or “b” depending on the filter
symmetry chosen. For example, if the FIR cell is configured
for an even symmetric filter with FWRD low and RVRS high,
the data shifting through the Forward Decimation Registers
would appear on the ALU output.
Table 3 details the ALU configurations, where “a” is the ALU
data input from the front decimation delay registers and “b” is
the ALU data from the back decimation delay registers.
TABLE 3. ALU CONFIGURATIONS
ALU
OUT SYMMETRY FWD RVS
DESCRIPTION
a+b 0 (Even)
0 0 Even Number of Taps, Even
Symmetry (Example 1)
+b 0 (Even)
0 1 Even Symmetry
+a 0 (Even)
1 0 Even Symmetry
- 0 (Even)
1 1 Even Symmetry
b-a 1 (Odd)
0 0 Even Number of Taps, Odd
Symmetry (Example 2)
+b 1 (Odd)
0 1 Odd Symmetry
-a 1 (Odd)
1 0 Odd Symmetry
- 1 (Odd)
1 1 Odd Symmetry
Coefficient Bank
The output of the ALU is multiplied by a coefficient from one
of 32 user programmable coefficient sets. Each set consists
of 8 coefficients (4 coefficients for FIR A and 4 for FIR B).
CSEL0-4 is used to select a coefficient set to be used.
8