HIP6004B_03 Datasheet, PDF (8/15 Pages) Intersil Corporation – Buck and Synchronous-Rectifier (PWM) Controller and Output Voltage Monitor

HIP6004B
TABLE 1. OUTPUT VOLTAGE PROGRAM
VID4
PIN NAME
VID3 VID2 VID1
VID0
NOMINAL OUTPUT
VOLTAGE DACOUT
VID4
PIN NAME
VID3 VID2 VID1
0
1
1
1
1
1.30
1
1
1
1
0
1
1
1
0
1.35
1
1
1
1
0
1
1
0
1
1.40
1
1
1
0
0
1
1
0
0
1.45
1
1
1
0
0
1
0
1
1
1.50
1
1
0
1
0
1
0
1
0
1.55
1
1
0
1
0
1
0
0
1
1.60
1
1
0
0
0
1
0
0
0
1.65
1
1
0
0
0
0
1
1
1
1.70
1
0
1
1
0
0
1
1
0
1.75
1
0
1
1
0
0
1
0
1
1.80
1
0
1
0
0
0
1
0
0
1.85
1
0
1
0
0
0
0
1
1
1.90
1
0
0
1
0
0
0
1
0
1.95
1
0
0
1
0
0
0
0
1
2.00
1
0
0
0
0
0
0
0
0
2.05
1
0
0
0
NOTE: 0 = connected to GND or V_SS, 1 = connected to V_DD through pull-up resistors.
VID0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
NOMINAL OUTPUT
VOLTAGE DACOUT
0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
V_IN
HIP6004B
UGATE
PHASE
LGATE
PGND
Q₁
L_O
V_OUT
Q₂
D₂
C_{IN CO}
RETURN
FIGURE 5. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
Figure 5 shows the critical power components of the converter.
To minimize the voltage overshoot the interconnecting wires
indicated by heavy lines should be part of ground or power
plane in a printed circuit board. The components shown in
Figure 5 should be located as close together as possible.
Please note that the capacitors C_IN and C_O each represent
numerous physical capacitors. Locate the HIP6004B within 3
inches of the MOSFETs, Q₁ and Q₂. The circuit traces for the
MOSFETs’ gate and source connections from the HIP6004B
must be sized to handle up to 1A peak current.
Figure 6 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS PIN and locate the capacitor, C_SS
close to the SS pin because the internal current source is
only 10µA. Provide local V_CC decoupling between V_CC and
GND pins. Locate the capacitor, C_BOOT as close as
practical to the BOOT and PHASE pins.
BOOT
D₁
C_BOOT
PHASE
HIP6004B
SS
V_{CC +12V}
+V_IN
Q₁ L_O
V_OUT
Q₂ ^CO
C_SS
GND
C_VCC
FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
Feedback Compensation
Figure 7 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V_OUT) is regulated to the Reference voltage level. The
error amplifier (Error Amp) output (V_E/A) is compared with
the oscillator (OSC) triangular wave to provide a pulse-
width modulated (PWM) wave with an amplitude of V_IN at
the PHASE node.
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