HIP6004A Datasheet, PDF (8/12 Pages) Intersil Corporation – Buck and Synchronous-Rectifier (PWM) Controller and Output Voltage Monitor

HIP6004A
together as possible. Please note that the capacitors C_IN
and C_O each represent numerous physical capacitors.
Locate the HIP6004A within 3 inches of the MOSFETs, Q₁
and Q₂. The circuit traces for the MOSFETs’ gate and
source connections from the HIP6004A must be sized to
handle up to 1A peak current.
Figure 6 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS PIN and locate the capacitor, C_ss
close to the SS pin because the internal current source is
only 10µA. Provide local V_CC decoupling between V_CC and
GND pins. Locate the capacitor, C_BOOT as close as practical
to the BOOT and PHASE pins.
BOOT
D₁
C_BOOT
HIP6004A ^PHASE
SS
V_{CC +12V}
C_SS
GND
C_VCC
+V_IN
Q₁ L_O
V_OUT
Q₂ ^CO
FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
Feedback Compensation
Figure 7 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V_OUT) is regulated to the Reference voltage level. The error
amplifier (Error Amp) output (V_E/A) is compared with the
oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of V_IN at the
PHASE node. The PWM wave is smoothed by the output
filter (L_O and C_O).
The modulator transfer function is the small-signal transfer
function of V_OUT/V_E/A. This function is dominated by a DC
Gain and the output filter (L_O and C_O), with a double pole
break frequency at F_LC and a zero at F_ESR. The DC Gain of
the modulator is simply the input voltage (V_IN) divided by the
peak-to-peak oscillator voltage ∆V_OSC.
Modulator Break Frequency Equations
F_LC=
------------------¹--------------------
2π • L_O • C_O
F_ESR= ₂----_π-----_•----_E-----_S-¹---_R------_•----_C-----_O--
The compensation network consists of the error amplifier
(internal to the HIP6004A) and the impedance networks Z_IN
and Z_FB. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f_0dB) and adequate phase margin. Phase margin
OSC
PWM
COMPARATOR
-
∆V_OSC
+
V_IN
DRIVER
DRIVER
L_O
PHASE _CO
V_OUT
Z_FB
V_E/A
-
Z_IN
+
ERROR ^REFERENCE
AMP
ESR
(PARASITIC)
DETAILED COMPENSATION COMPONENTS
C₂
C_{1 R2}
Z_FB
V_OUT
Z_IN
C₃ R₃
COMP
R₁
-
FB
+
HIP6004A
DACOUT
FIGURE 7. VOLTAGE-MODE BUCK CONVERTER COMPEN-
SATION DESIGN
is the difference between the closed loop phase at f_0dB and
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R₁, R₂,
R₃, C₁, C₂, and C₃) in Figure 7. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R₂/R₁) for desired converter bandwidth
2. Place 1^ST Zero Below Filter’s Double Pole (~75% F_LC)
3. Place 2^ND Zero at Filter’s Double Pole
4. Place 1^ST Pole at the ESR Zero
5. Place 2^ND Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
Compensation Break Frequency Equations
F_Z1 = -₂---_π-----_•----_R---¹--₂----_•-----_C----₁-
F_Z2 = -₂---_π-----_•----₍---_R----₁-----+¹-----_R----₃----₎---_•----_C-----₃-
F_P1
=
-------------------------¹---------------------------
2
π
•
R₂
•



C^-C----₁₁^{-----+•----CC-----22-}_{}
F_P2 = ₂----_π-----_•----_R---¹--₃----_•-----_C----₃-
Figure 8 shows an asymptotic plot of the DC-DC
converter’s gain vs. frequency. The actual Modulator Gain
has a high gain peak due to the high Q factor of the output
filter and is not shown in Figure 8. Using the above
guidelines should give a Compensation Gain similar to the
curve plotted. The open loop error amplifier gain bounds
the compensation gain. Check the compensation gain at
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