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HD-15530_1I Datasheet, PDF (8/13 Pages) Intersil Corporation – CMOS Manchester Encoder-Decoder
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HD-15530
AC Electrical Specifications VCC = 5V ±10%, TA = -40oC to +85oC (HD-15530-9)
TA = -55oC to +125oC (HD-15530-8)
PARAMETER
SYMBOL
(NOTE 2)
TEST CONDITIONS
LIMITS
MIN
MAX
UNITS
ENCODER TIMING
Encoder Clock Frequency
FEC
VCC = 4.5V and 5.5V, CL = 50pF
-
15
MHz
Send Clock Frequency
FESC
VCC = 4.5V and 5.5V, CL = 50pF
-
2.5
MHz
Encoder Data Rate
FED
VCC = 4.5V and 5.5V, CL = 50pF
-
1.25
MHz
Master Reset Pulse Width
TMR
VCC = 4.5V and 5.5V, CL = 50pF
150
-
ns
Shift Clock Delay
TE1
VCC = 4.5V and 5.5V, CL = 50pF
-
125
ns
Serial Data Setup
TE2
VCC = 4.5V and 5.5V, CL = 50pF
75
-
ns
Serial Data Hold
TE3
VCC = 4.5V and 5.5V, CL = 50pF
75
-
ns
Enable Setup
TE4
VCC = 4.5V and 5.5V, CL = 50pF
90
-
ns
Enable Pulse Width
TE5
VCC = 4.5V and 5.5V, CL = 50pF
100
-
ns
Sync Setup
TE6
VCC = 4.5V and 5.5V, CL = 50pF
55
-
ns
Sync Pulse Width
TE7
VCC = 4.5V and 5.5V, CL = 50pF
150
-
ns
Send Data Delay
TE8
VCC = 4.5V and 5.5V, CL = 50pF
0
50
ns
Bipolar Output Delay
TE9
VCC = 4.5V and 5.5V, CL = 50pF
-
130
ns
Enable Hold
TE10
VCC = 4.5V and 5.5V, CL = 50pF
10
-
ns
Sync Hold
TE11
VCC = 4.5V and 5.5V, CL = 50pF
95
-
ns
DECODER TIMING
Decoder Clock Frequency
FDC
VCC = 4.5V and 5.5V, CL = 50pF
-
15
Decoder Data Rate
FDD
VCC = 4.5V and 5.5V, CL = 50pF
-
1.25
Decoder Reset Pulse Width
TDR
VCC = 4.5V and 5.5V, CL = 50pF
150
-
Decoder Reset Setup Time
TDRS
VCC = 4.5V and 5.5V, CL = 50pF
75
-
Decoder Reset Hold Time
TDRH
VCC = 4.5V and 5.5V, CL = 50pF
10
-
Master Reset Pulse
TMR
VCC = 4.5V and 5.5V, CL = 50pF
150
-
Bipolar Data Pulse Width
TD1
VCC = 4.5V and 5.5V, CL = 50pF
TDC + 10
-
(Note 1)
MHz
MHz
ns
ns
ns
ns
ns
One Zero Overlap
TD3
VCC = 4.5V and 5.5V, CL = 50pF
-
TDC - 10
ns
(Note 1)
Sync Delay (ON)
TD6
VCC = 4.5V and 5.5V, CL = 50pF
-20
110
ns
Take Data Delay (ON)
TD7
VCC = 4.5V and 5.5V, CL = 50pF
0
110
ns
Serial Data Out Delay
TD8
VCC = 4.5V and 5.5V, CL = 50pF
-
80
ns
Sync Delay (OFF)
TD9
VCC = 4.5V and 5.5V, CL = 50pF
0
110
ns
Take Data Delay (OFF)
TD10
VCC = 4.5V and 5.5V, CL = 50pF
0
110
ns
Valid Word Delay
TD11
VCC = 4.5V and 5.5V, CL = 50pF
0
110
ns
NOTES:
1. TDC = Decoder clock period = 1/FDC
2. AC Testing as follows: Input levels: VIH = 70% VCC, VIL = 20% VCC; Input rise/fall times driven at 1ns/V; Timing Reference levels: 1.5V;
Output load: CL = 50pF.
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