EL7551_06 Datasheet, PDF (8/9 Pages) Intersil Corporation – Monolithic 1Amp DC:DC Step-down Regulator

EL7551
LX pin rises the positive plate of capacitor CVHI follows and
eventually reaches a value of VDRV+VIN, typically 10V, for
VDRV=VIN=5V. This voltage is then level shifted and used to
drive the gate of the high-side FET, via the VHI pin. A value
of 0.1µF for CVHI is recommended.
Reference
A 1.5% temperature compensated bandgap reference is
integrated in the EL7551. The external VREF capacitor acts
as the dominant pole of the amplifier and can be increased
in size to maximize transient noise rejection. A value of
0.1µF is recommended.
Oscillator
The system clock is generated by an internal relaxation
oscillator with a maximum duty-cycle of approximately 95%.
Operating frequency can be adjusted through the COSC pin
or can be driven by an external source. If the oscillator is
driven by an external source care must be taken in selecting
the ramp amplitude. Since CSLOPE value is derived from
the COSC ramp, changes to COSC ramp will change the
CSLOPE compensation ramp which determine the open-
loop gain of the system.
When external synchronization is required, always choose
C_OSC such that the free-running frequency is at least 20%
lower than that of sync source to accommodate component
and temperature variations. Figure 1 shows a typical
connection.
External
Oscillator
100pF BAT54S
1
16
2
15
3
14
6
11
7
10
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9
EL7551
FIGURE 1. OSCILLATOR SYNCHRONIZATION
Thermal Shut-down
An internal temperature sensor continuously monitors die
temperature. In the event that die temperature exceeds the
thermal trip-point, the system is in fault state and will be shut
down. The upper and low trip-points are set to 135°C and
115°C respectively.
Start-up Delay
A capacitor can be added to the EN pin to delay the
converter start-up (Figure 2) by utilizing the pull-up current.
The delay time is approximately:
t_d(ms) = 1200 × C(µF)
1
16
2
15
3
14
6
11
7
10
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9
C
EL7551
V_OUT
V_IN
V_O
t_d
TIME
FIGURE 2. START-UP DELAY
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