CD4047BMS Datasheet, PDF (8/15 Pages) Intersil Corporation – CMOS Low-Power Monostable/Astable Multivibrator

Logic Diagrams (Continued)
*
ASTABLE 5
*
ASTABLE 4
*
+TRIGGER 8
*
-TRIGGER 6
VDD
FF1
DQ
CL
CL
R1 R2
CD4047BMS
*
RETRIGGER 12
**
VDD 3 ^RC
COMMON
CTC 1
2 RTC
OSC
OUT
13
VDD 14
VSS 7
EXTERNAL
*
9
RESET
* ^{INPUTS PROTECTED}
BY CMOS
PROTECTION
NETWORK
S
DQ
FF2
VSS
CL
CL Q
R
DQ
FF3
CL
CL
R1 R2
S
DQ
FF4
CL
CL
R
VDD
VSS
CAUTION: Terminal 3 is more sensitive
to static electrical discharge. Extra
handling precautions are recommended.
FIGURE 2. CD4047BMS LOGIC DIAGRAM
** ^SPECIAL
RC COMMON
PROTECTION
NETWORK
10 Q
11 Q
VDD
VSS
CL
CL ^{R2 R1}
DQ
CL
CL
R1 R2
FF1, FF3
p
D
n
CL
p
n
R1 R2
CL
CL
p
n
Q
CL
p
n
CL
CL
(a)
S
DQ
CL
CL
RQ
FF2, FF4
CL _S
p
D
n
CL
Q
CL
S
p
n
Q
CL
CL
CL
p
n
R
CL
(b)
p
n
R
CL
FIGURE 3. DETAIL LOGIC DIAGRAM FOR FLIP-FLOPS FF1 AND FF3 (a) AND FOR FLIP-FLOPS FF2 AND FF4 (b)
7-904