X4005S8IZ-27 Datasheet, PDF (7/16 Pages) Intersil Corporation – Selectable watchdog timer

X4003, X4005
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the control register
during a write operation. This bit is a volatile latch that
powers up in the LOW (disabled) state. While the WEL bit is
LOW, writes the control register will be ignored (no
acknowledge will be issued after the data byte). The WEL bit
is set by writing a “1” to the WEL bit and zeroes to the other
bits of the control register. Once set, WEL remains set until
either it is reset to 0 (by writing a “0” to the WEL bit and
zeroes to the other bits of the control register) or until the
part powers up again. Writes to the WEL bit do not cause a
nonvolatile write cycle, so the device is ready for the next
operation immediately after the stop condition.
WD1, WD0: Watchdog Timer Bits
The bits WD1 and WD0 control the period of the watchdog
timer. The options are shown in the following:
WD1
0
0
1
1
WD0
0
1
0
1
WATCHDOG TIME-OUT PERIOD
1.4s
600ms
200ms
Disabled (factory setting)
Writing to the Control Register
Changing any of the nonvolatile bits of the control register
requires the following steps:
• Write a 02H to the control register to set the write enable
latch (WEL). This is a volatile operation, so there is no
delay after the write. (Operation preceeded by a start and
ended with a stop.)
• Write a 06H to the control register to set both the register
write enable latch (RWEL) and the WEL bit. This is also a
volatile cycle. The zeros in the data byte are required.
(Operation preceeded by a start and ended with a stop.)
• Write a value to the control register that has all the control
bits set to the desired state. This can be represented as
0xy0 0010 in binary, where xy are the WD bits. (Operation
preceeded by a start and ended with a stop.) Since this is
a nonvolatile write cycle it will take up to 10ms to
complete. The RWEL bit is reset by this cycle and the
sequence must be repeated to change the nonvolatile bits
again. If bit 2 is set to ‘1’ in this third step (0xy0 0110) then
the RWEL bit is set, but the WD1 and WD0 bits remain
unchanged. Writing a second byte to the control register is
not allowed. Doing so aborts the write operation and
returns a NACK.
• A read operation occurring between any of the previous
operations will not interrupt the register write operation.
• The RWEL bit cannot be reset without writing to the
nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write
protected block.
To illustrate, a sequence of writes to the device consisting of
[02H, 06H, 02H] will reset all of the nonvolatile bits in the
control register to 0. A sequence of [02H, 06H, 06H] will
leave the nonvolatile bits unchanged and the RWEL bit
remains set.
Serial Interface
Serial Interface Conventions
The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the slave.
The master always initiates data transfers, and provides the
clock for both transmit and receive operations. Therefore,
the devices in this family operate as slaves in all
applications.
Serial Clock and Data
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions. See Figure 6.
SCL
SDA
DATA STABLE
DATA CHANGE
DATA STABLE
FIGURE 6. VALID DATA CHANGES ON THE SDA BUS
7
FN8113.2
June 30, 2008