QLX4600-SL30 Datasheet, PDF (7/23 Pages) Intersil Corporation – Quad Lane Extender

QLx4600-SL30
Electrical Specifications Typical values are at V_DD = 1.2V, T_A = +25°C, and V_IN = 800mV_P-P, unless otherwise noted.
V_DD = 1.1V to 1.3V, T_A = 0°C to +70°C. (Continued)
PARAMETERS
SYMBOL
CONDITION
MIN TYP MAX UNITS NOTES
Line Silence-to-Data
Response Time
t_SD
Time to transition from line silence mode
(muted output) to active data on 20m
24AWG standard twin-axial cable at 5Gb/s
20
ns
8, 11
Time from first bit of ALIGN(0) for SAS
OOB signaling to 450mV_P-P output;
Meritec 24AWG 20m; 3Gb/s
19
ns
12
Timing Difference (SAS)
|t _DS - t _SD| For SAS OOB signaling support; Meritec
24AWG 20m
5
ns
12
NOTES:
3. After channel loss, differential amplitudes at QLx4600-SL30 inputs must meet the input voltage range specified in “Absolute
Maximum Ratings” on page 5.
4. Temperature = +25°C, V_DD = 1.2V.
5. Output residual jitter is the difference between the total jitter at the lane extender output and the total jitter of the transmitted
signal (as measured at the input to the channel). Total jitter (TJ) is DJ_PP + 14.1 x RJ_RMS.
6. Measured using a PRBS 2⁷-1 pattern. Deterministic jitter at the input to the lane extender is due to frequency-dependent,
media-induced loss only.
7. Rise and fall times measured using a 1GHz clock with a 20ps edge rate.
8. For active data mode, cable input amplitude is 400mV_P-P (differential) or greater. For line silence mode, cable input amplitude
is 20mV_P-P (differential) or less.
9. Measured differentially across the data source.
10. During line silence, transmitter noise in excess of this voltage range may result in differential output amplitudes from the
QLx4600 that are greater than 20mV_P-P.
11. The data pattern preceding line silence mode is comprised of the PCIe electrical idle ordered set (EIOS). The data pattern
following line silence mode is comprised of the PCIe electrical idle exit sequence (EIES).
12. The data pattern preceding or following line silence mode is comprised of the SAS-2 ALIGN (0) sequence for OOB signaling at
3Gb/s, and amplitude of 800mV_P-P.
Serial Bus Timing Characteristics
PARAMETER
SYMBOL
CONDITION
CLK Setup Time
t_SCK From the falling edge of ENB
DI Setup Time
t_SDI Prior to the rising edge of CLK
DI Hold Time
t_HDI From the rising edge of CLK
ENB ‘HIGH’
t_HEN From the falling edge of the last data bit’s CLK
Boost Setting Operational
t_D
From ENB ‘HIGH’
DO Hold Time
t_CQ
From the rising edge of CLK to DO transition
Clock Rate
f_CLK Reference clock for serial bus EQ programming
MIN
10
10
6
10
12
TYP
MAX UNITS
ns
ns
ns
ns
10
ns
ns
20
MHz
7
FN6981.1
November 19, 2009