ISL97671A_15 Datasheet, PDF (7/28 Pages) Intersil Corporation – 6-Channel SMBus/I2C or PWM Dimming LED Driver with Phase Shift Control

ISL97671A
Electrical Specifications V_IN = 12V, EN = 5V, R_SET = 20.1kΩ, unless otherwise noted. Boldface limits apply over the operating
temperature range, -40°C to +85°C. (Continued)
PARAMETER
DESCRIPTION
CONDITION
MIN
MAX
(Note 8) TYP (Note 8) UNIT
FAULT PIN
I_FAULT
V_FAULT
LXstart_thres
Fault Pull-down Current
Fault Clamp Voltage with Respect to V_IN
LX Start-up Threshold
V_IN = 12V
V_IN = 12, V_IN - V_FAULT
12
21
30
µA
6
7
8.3
V
0.9
1.2
V
ILXStart-up LX Start-up Current
SMBus/I²C INTERFACE
1
3.5
5
mA
V_IL
Guaranteed Range for Data, Clock Input Low
Voltage
0.8
V
V_IH
Guaranteed Range for Data, Clock Input High
Voltage
V_OL
SMBus/I²C Data line Logic Low Voltage
I_PULLUP = 4mA
I_LEAK
Input Leakage On SMBData/SMBClk
Measured at 4.8V
SMBus/I²C TIMING SPECIFICATIONS
1.5
VDD
V
0.17
V
-10
10
µA
t_EN-SMB/I²C Minimum Time Between EN high and
1µF capacitor on VDC
2
ms
SMBus/I²C Enabled
PWS
Pulse Width Suppression on
SMBCLK/SMBDAT
0.15
0.45
µs
f_SMB
SMBus/I²C Clock Frequency
t_BUF
Bus Free Time Between Stop and Start
Condition
400
kHz
1.3
µs
t_HD:STA
Hold Time After (Repeated) START Condition.
After this Period, the First Clock is Generated
0.6
µs
t_SU:STA
Repeated Start Condition Setup Time
0.6
µs
t_SU:STO
Stop Condition Setup Time
0.6
µs
t_HD:DAT
Data Hold Time
300
ns
t_SU:DAT
Data Setup Time
100
ns
t_LOW
Clock Low Period
1.3
µs
t_HIGH
Clock High Period
0.6
µs
t_F
Clock/data Fall Time
300
ns
t_R
Clock/data Rise Time
300
ns
NOTES:
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
9. At maximum V_IN of 26.5V, minimum V_OUT is limited 28V.
7
FN7709.3
November 30, 2012