ISL76322_1108 Datasheet, PDF (7/13 Pages) Intersil Corporation – 16-Bit Long-Reach Video Automotive Grade SERDES

ISL76322
Electrical Specifications Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V_,
VDD_TX = VDD_P = VDD_AN = 3.3V, T_A = +25°C, Ref_Res = 3.16kΩ, High-speed AC-coupling capacitor = 27nF. Boldface limits apply over the operating
temperature range, -40°C to +105°C. (Continued)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
(Note 10) TYP (Note 10) UNITS
Output Rise and Fall Times
SERIALIZER PARALLEL INTERFACE
t_OR/t_OF
Slew rate control set to min
C_L = 8pF
Slew rate control set to max, C_L = 8pF
1
ns
4
ns
PCLK_IN Frequency
f_IN
PCLK_IN Duty Cycle
t_IDC
Parallel Input Setup Time
t_IS
Parallel Input Hold Time
t_IH
DESERIALIZER PARALLEL INTERFACE
6
50 MHz
40 50 60
%
3.5
ns
1.0
ns
PCLK_OUT Frequency
PCLK_OUT Duty Cycle
PCLK_OUT Period Jitter (rms)
PCLK_OUT Spread Width
PCLK_OUT to Parallel Data Outputs
(includes Sync and DE pins)
f_OUT
t_ODC
t_OJ
t_OSPRD
t_DV
Clock randomizer off
Clock randomizer on
Relative to PCLK_OUT,
(Note 9)
6
50 MHz
50
%
0.5
%t_PCLK
±20
%t_PCLK
-1.0
5.5
ns
Deserializer Output Latency
t_CPD Inherent in the design
DESERIALIZER REFERENCE CLOCK (REF_CLK IS FED INTO PCLK_IN)
4
9
14 PCLK
REF_CLK Lock Time
REF_CLK to PCLK_OUT Maximum Frequency Offset
t_PLL
PCLK_OUT is the
recovered clock
100
µs
1500 5000
ppm
HIGH-SPEED TRANSMITTER
HS Differential Output Voltage, Transition Bit
HS Differential Output Voltage, Non-Transition Bit
HS Generated Output Common Mode Voltage
HS Common Mode Serializer-Deserializer Voltage
Difference
VOD_TR
TXCN = 0x00
TXCN = 0x0F
TXCN = 0xF0
TXCN = 0xFF
VOD_NTR TXCN = 0x00
TXCN = 0x0F
TXCN = 0xF0
TXCN = 0xFF
V_OCM
ΔV_CM
650 800 900 mV_P-P
900
mV_P-P
1100
mV_P-P
1300
mV_P-P
650 800 900 mV_P-P
900
mV_P-P
430
mV_P-P
600
mV_P-P
2.35
V
10 20
mV
HS Differential Output Impedance
HS Output Latency
HS Output Rise and Fall Times
HS Differential Skew
HS Output Random Jitter
HS Output Deterministic Jitter
R_OUT
t_LPD
t_R/t_F
t_SKEW
t_RJ
t_DJ
Inherent in the design
20% to 80%
PCLK_IN = 45MHz
PCLK_IN = 45MHz
80 100 120
Ω
4
7
10 PCLK
150
ps
<10
ps
6
ps_rms
25
ps_P-P
7
August 15, 2011
FN7611.1