ISL6742_14 Datasheet, PDF (7/18 Pages) Intersil Corporation – Advanced Double-Ended PWM Controller

ISL6742
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 2,
“Typical Application - Telecom Primary Side Control Half-Bridge Converter with Synchronous Rectification” on
page 3 and “Typical Application - High Voltage Input Secondary Side Control Full-Bridge Converter” on page 4.
9V < VDD < 20V, RTD = 10.0kΩ, CT = 470pF, T_A = -40°C to +105°C, Typical values are at T_A = +25°C.
Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature
limits established by characterization and are not production tested. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
CT Valley Voltage
Static Threshold
0.75
0.80
0.88
V
CT Peak Voltage
Static Threshold
2.75
2.80
2.88
V
CT Pk-Pk Voltage
Static Value
1.92
2.00
2.05
V
RTD Voltage
1.97
2.00
2.03
V
OUTPUT
High Level Output Voltage (VOH)
I_OUT = -10mA, VDD - VOH
-
0.5
1.0
V
Low Level Output Voltage (VOL)
I_OUT = 10mA, VOL - GND
-
0.5
1.0
V
Rise Time
C_OUT = 220pF, VDD = 15V (Note 3)
-
110
200
ns
Fall Time
C_OUT = 220pF, VDD = 15V (Note 3)
-
90
150
ns
UVLO Output Voltage Clamp
VDD = 7V, I_LOAD = 1mA (Note 5)
-
-
1.25
V
Output Delay/Advance Range
OUTAN/OUTBN Relative to OUTA/OUTB
V_ADJ = 2.50V (Note 3)
V_ADJ < 2.425V
-
-
3
ns
-40
-
-300
ns
V_ADJ > 2.575V
40
-
300
ns
Delay Control Voltage Range
OUTAN/OUTBN Relative to OUTA/OUTB
OUTxN Delayed
OUTx Delayed
2.575
-
5.000
V
0
-
2.425
V
VADJ Delay Time
T_A = +25°C (OUTx Delayed) (Note 6)
VADJ = 0
280
300
320
ns
VADJ = 0.5V
92
105
118
ns
VADJ = 1.0V
61
70
80
ns
VADJ = 1.5V
48
55
65
ns
VADJ = 2.0V
41
50
58
ns
T_A = +25°C (OUTxN Delayed)
VADJ = VREF
280
300
320
ns
VADJ = VREF - 0.5V
86
100
114
ns
VADJ = VREF - 1.0V
59
68
77
ns
VADJ = VREF - 1.5V
47
55
62
ns
VADJ = VREF - 2.0V
41
48
55
ns
THERMAL PROTECTION
Thermal Shutdown
(Note 3)
130
140
150
°C
Thermal Shutdown Clear
(Note 3)
115
125
135
°C
Hysteresis, Internal Protection
(Note 3)
-
15
-
°C
NOTES:
3. Limits established by characterization and are not production tested.
4. This is the maximum duty cycle achievable using the specified values of RTD and CT. Larger or smaller maximum duty cycles may be obtained
using other values for these components. See Equations 1 through 3.
5. Adjust VDD below the UVLO stop threshold prior to setting at 7V.
6. When OUTx is delayed relative to OUTLxN (VADJ < 2.425V), the delay duration as set by VADJ should not exceed 90% of the CT discharge time
(deadtime) as determined by CT and RTD.
7
FN9183.2
October 31, 2008