ISL6721A Datasheet, PDF (7/24 Pages) Intersil Corporation – Flexible Single-ended Current Mode PWM Controller

ISL6721A
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
schematic on page 3 and page 4. 9V < V_CC = V_C < 20V, RT = 11kΩ, CT = 330 pF. Typical values are at
T_A = +25°C. Boldface limits apply over the operating temperature range, -40°C to +105°C. (Continued)
PARAMETER
TEST CONDITIONS
MIN
MAX
(Note 9)
TYP
(Note 9)
UNITS
Blanking Time
(Note 10)
30
60
100
ns
Gain, A_CS
ERROR AMPLIFIER
V_SLOPE = 0V, V_FB = 2.3V,
V_ISET = 0.35V, 1.5V
A_CS = ΔISET/ΔISENSE
0.77
0.79
0.81
V/V
Open Loop Voltage Gain
(Note 10)
60
90
-
dB
Gain-Bandwidth Product
(Note 10)
-
15
-
MHz
Reference Voltage Initial Accuracy
V_FB = COMP, T_A = +25°C
(Note 10)
2.465
2.515
2.565
V
Reference Voltage
COMP to PWM Gain, A_COMP
COMP to PWM Offset
V_FB = COMP
COMP = 4V, T_A = +25°C
COMP = 4V (Note 10)
2.44
2.515
2.590
V
0.31
0.33
0.35
V/V
0.51
0.75
0.88
V
FB Input Bias Current
COMP Sink Current
COMP Source Current
COMP VOH
COMP VOL
PSRR
V_FB = 0V
-2
0.1
2
µA
COMP = 1.5V, V_FB = 2.7V
2
6
-
mA
COMP = 1.5V, V_FB = 2.3V
-0.25
-0.5
-
mA
V_FB = 2.3V
4.25
4.4
5.0
V
V_FB = 2.7V
0.4
0.8
1.2
V
Frequency = 120Hz (Note 10)
60
80
-
dB
SS Clamp, V_COMP
OSCILLATOR
SS = 2.5V, V_FB = 0V, ISET = 2V
2.4
2.5
2.6
V
Frequency Accuracy
289
318
347
kHz
Frequency Variation with V_CC
Temperature Stability
T = +105°C (f_20V - f_9V)/f_9V
T = -40°C (f_20V -f_9V)/f_9V
(Note 10)
-
2
3
%
2
3
-
8
-
%
Maximum Duty Cycle
(Note 12)
68
75
81
%
Comparator High Threshold - Free Running
-
3.00
-
V
Comparator High Threshold - with External SYNC (Note 10)
-
4.00
-
V
Comparator Low Threshold
-
1.50
-
V
Discharge Current
0°C to +105°C
-40°C to +105°C
0.75
1.0
1.2
mA
0.70
1.0
1.2
SYNCHRONIZATION
Input High Threshold
-
-
2.5
V
Input Pulse Width
25
-
-
ns
Input Frequency Range
(Note 10)
0.65 x Free
-
Running
(Period)
1.0
MHz
Input Impedance
-
4.5
-
kΩ
VOH
VOL
SYNC Advance
R_LOAD = 4.5kΩ
2.5
-
-
V
R_LOAD = open
-
-
0.1
V
SYNC rising edge to GATE falling
-
edge, C_GATE = C_SYNC = 100pF
25
55
ns
7
FN6797.0
August 23, 2011