ISL6615AIRZ-T Datasheet, PDF (7/12 Pages) Intersil Corporation – High-Frequency 6A Sink Synchronous MOSFET Drivers with Protection Features

ISL6615A
Power-On Reset (POR) Function
During initial start-up, the VCC voltage rise is monitored. Once the
rising VCC voltage exceeds 6.4V (typically), operation of the driver
is enabled and the PWM input signal takes control of the gate
drives. If VCC drops below the falling threshold of 5.0V (typically),
operation of the driver is disabled.
Pre-POR Overvoltage Protection
Prior to VCC exceeding its POR level, the upper gate is held low
and the lower gate is controlled by the overvoltage protection
circuits. The upper gate driver is powered from PVCC and will be
held low when a voltage of 2.75V or higher is present on PVCC as
VCC surpasses its POR threshold. The PHASE is connected to the
gate of the low side MOSFET (LGATE), which provides some
protection to the microprocessor if the upper MOSFET(s) is
shorted during start-up, normal, or shutdown conditions. For
complete protection, the low side MOSFET should have a gate
threshold well below the maximum voltage rating of the
load/microprocessor.
Internal Bootstrap Device
Both drivers feature an internal bootstrap Schottky diode. Simply
adding an external capacitor across the BOOT and PHASE pins
completes the bootstrap circuit. The bootstrap function is also
designed to prevent the bootstrap capacitor from overcharging
due to the large negative swing at the trailing-edge of the PHASE
node. This reduces voltage stress on the boot to phase pins.
The bootstrap capacitor must have a maximum voltage rating
above PVCC + 5V and its capacitance value can be chosen from
Equation 1:
C_{BOOT_CAP} ≥ _Δ-----_V---_B-^Q---_O-^G--_O--^A--_T-^T--_{_}-^E--_C---_A---_P--
(EQ. 1)
Q_GATE=
Q_{-----G---1-----}•_----P_----V_----C_----C_--
V_GS1
•
N_Q
1
where Q_G1 is the amount of gate charge per upper MOSFET at
V_GS1 gate-source voltage and N_Q1 is the number of control
MOSFETs. The ΔV_{BOOT_CAP} term is defined as the allowable
droop in the rail of the upper gate drive.
As an example, suppose two IRLR7821 FETs are chosen as the
upper MOSFETs. The gate charge, Q_G, from the data sheet is
10nC at 4.5V (V_GS) gate-source voltage. Then the Q_GATE is
calculated to be 53nC for PVCC = 12V. We will assume a 200mV
droop in drive voltage over the PWM cycle. We find that a
bootstrap capacitance of at least 0.267µF is required. The next
larger standard value capacitance is 0.33µF. A good quality
ceramic capacitor is recommended.
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2 _20nC
Q_GATE = 100nC
50nC
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
ΔV_{BOOT_CAP} (V)
FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Gate Drive Voltage Versatility
The ISL6615A provides the user with flexibility in choosing the
gate drive voltage for efficiency optimization. The ISL6615A ties
the upper and lower drive rails together. Simply applying a
voltage from +4.5V up to 13.2V on PVCC sets both gate drive rail
voltages simultaneously, while VCC’s operating range is from
+6.8V up to 13.2V.
Power Dissipation
Package power dissipation is mainly a function of the switching
frequency (F_SW), the output drive impedance, the external gate
resistance and the selected MOSFET’s internal gate resistance and
total gate charge. Calculating the power dissipation in the driver for
a desired application is critical to ensure safe operation. Exceeding
the maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
dissipation for the SO8 package is approximately 800mW at room
temperature, while the power dissipation capacity in the DFN
package (with an exposed heat escape pad) is more than 1.5W. The
DFN package is more suitable for high frequency applications. See
“Layout Considerations” on page 8 for thermal transfer
improvement suggestions. When designing the driver into an
application, it is recommended that the following calculation is used
to ensure safe operation at the desired frequency for the selected
MOSFETs. The total gate drive power losses due to the gate charge
of MOSFETs and the driver’s internal circuitry and their
corresponding average driver current can be estimated with
Equations 2 and 3, respectively:
P_{Qg_TOT} = P_{Qg_Q1} + P_{Qg_Q2} + I_Q • VCC
(EQ. 2)
P _{Q g _Q1}
=
Q_{-----G---1-----}•_----P_----V_----C_----C_----²_-
V_GS1
•
F_S
W
•
N_Q
1
P _{Q g _Q2}
=
Q_{-----G---2-----}•_----P_----V_----C_----C_----²_-
V_GS2
•
F_SW
•
N_Q2
I_DR
=
⎛
⎜
⎝
Q_{-----G---1-----}•_----P_----V_----C_----C_-----•_----N_----Q----1--
V_GS1
+
-^Q----^G---²-----^•----^P-_V---^V_G----^C_S----₂^C-----^•----^N----^Q----²--_{⎠⎟⎞}
• F_SW + I_Q
(EQ. 3)
7
FN6608.2
April 13, 2012