ISL6557 Datasheet, PDF (7/17 Pages) Intersil Corporation – Multi-Phase PWM Controller for Core-Voltage Regulation

ISL6557
Figure 2 (previous page) illustrates the multiplicative effect
on output ripple frequency. The three channel currents (IL1,
IL2, and IL3), combine to form the AC ripple current and the
DC load current. The ripple component has three times the
ripple frequency of each individual channel current. Each
PWM pulse is terminated 1/3 of a cycle, or 1.33µs, after the
PWM pulse of the previous phase. The peak-to-peak current
waveforms for each phase is about 7A, and the dc
components of the inductor currents combine to feed the load.
To understand the reduction of ripple current amplitude in
the multi-phase circuit, examine the equation representing
an individual channel’s peak-to-peak inductor current.
I_{L, PP =}
(_---V_{----I--N-----–-----}V_{----O-----U----T---})_----V_{----O----U-----T-}
L
f_S
V
I
N
(EQ. 1)
In Equation 1, V_IN and V_OUT are the input and output
voltages respectively, L is the single-channel inductor value,
and f_S is the switching frequency.
I_PP=
(_---V_{----I--N-----–-----}N_------V_{----O-----U----T---})_----V_{----O----U-----T-}
L f_S V_IN
(EQ. 2)
The output capacitors conduct the ripple component of the
inductor current. In the case of multi-phase converters, the
capacitor current is the sum of the ripple currents from each
of the individual channels. Compare Equation 1 to the
expression for the peak-to-peak current after the summation
of N symmetrically phase-shifted inductor currents in
Equation 2. Peak-to-peak ripple current decreases by an
amount proportional to the number of channels. Output-
voltage ripple is a function of capacitance, capacitor
equivalent series resistance (ESR), and inductor ripple
current. Reducing the inductor ripple current allows the
designer to use fewer or less costly output capacitors.
INPUT-CAPACITOR CURRENT, 10A/DIV
CHANNEL 3
INPUT CURRENT
10A/DIV
CHANNEL 2
INPUT CURRENT
10A/DIV
CHANNEL 1
INPUT CURRENT
10A/DIV
1µs/DIV
FIGURE 3. CHANNEL INPUT CURRENTS AND INPUT-
CAPACITOR RMS CURRENT FOR 3-PHASE
CONVERTER
Another benefit of interleaving is to reduce input ripple
current. Input capacitance is determined in part by the
maximum input ripple current. Multi-phase topologies can
improve overall system cost and size by lowering input ripple
current and allowing the designer to reduce the cost of input
capacitance. The example in Figure 3 illustrates input
currents from a three-phase converter combining to reduce
the total input ripple current.
The converter depicted in Figure 3 delivers 36A to a 1.5V
load from a 12V input. The rms input capacitor current is
5.9A. Compare this to a single-phase converter also down
12V to 1.5V at 36A. The single-phase converter has 11.9A
rms input capacitor current. The single-phase converter
must use an input capacitor bank with twice the rms current
capacity as the equivalent three-phase converter.
Figures 15, 16 and 17 the section entitled Input Capacitor
Selection can be used to determine the input-capacitor rms
current based on load current, duty cycle, and the number of
channels. They are provided as aids in determining the
optimal input capacitor solution. Figure 18 shows the single
phase input-capacitor rms current for comparisson.
PWM OPERATION
The number of active channels selected determines the
timing for each channel. By default, the timing mode for the
ISL6557 is 4-phase. The designer can select 2-phase timing
by connecting PWM3 to VCC or 3-phase timing by
connecting PWM4 to VCC.
One switching cycle for the ISL6557 is defined as the time
between PWM1 pulse termination signals (the internal signal
that initiates a falling edge on PWM1). The cycle time is the
inverse of the switching frequency selected by the resistor
connected between the FS pin and ground (see Switching
Frequency). Each cycle begins when a clock signal
commands the channel-1 PWM output to go low. This
signals the channel-1 MOSFET driver to turn off the channel-1
upper MOSFET and turn on the channel-1 synchronous
MOSFET. If two-channel operation is selected, the PWM2
pulse terminates 1/2 of a cycle later. If three channels are
selected the PWM2 pulse terminates 1/3 of a cycle after
PWM1, and the PWM3 output will follow after another 1/3 of
a cycle. When four channels are selected, the pulse-
termination times are spaced in 1/4 cycle increments.
Once a channel’s PWM pulse terminates, it remains low for
a minimum of 1/4 cycle. This forced off time is required to
assure an accurate current sample as described in Current
Sensing. Following the 1/4-cycle forced off time, the
controller enables the PWM output. Once enabled, the PWM
output transitions high when the sawtooth signal crosses the
adjusted error-amplifier output signal, V_COMP as illustrated
in Figures 1 and 5. This is the signal for the MOSFET driver
to turn off the synchronous MOSFET and turn on the upper
MOSFET. The output will remain high until the clock signals
the beginning of the next cycle by commanding the PWM
pulse to terminate.
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