ISL6405 Datasheet, PDF (7/13 Pages) Intersil Corporation – Dual Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-top Box Designs

ISL6405
Functional Pin Description
SYMBOL
SDA
SCL
VSW1, 2
PGND1, 2
CS1, 2
SGND
AGND
TCAP1, 2
BYPASS
DSQIN1, 2
VCC
GATE1, 2
VO1, 2
ADDR
COMP1, 2
FB1, 2
CPVOUT,
CPSWIN,
CPSWOUT
SEL18V1, 2
FUNCTION
Bidirectional data from/to I²C bus.
Clock from I²C bus.
Input of the linear post-regulator.
Dedicated ground for the output gate driver of
respective PWM.
Current sense input; connect Rsc at this pin for
desired over current value for respective PWM.
Small signal ground for the IC.
Analog ground for the IC.
Capacitor for setting rise and fall time of the output
of LNB A and LNB B respectively. Use this
capacitor value 1µF or higher.
Bypass capacitor for internal 5V.
When HIGH enables internal 22kHz modulation for
LNB A and LNA B respectively, Use this pin for
tone enable function for LNB A and LNB B.
Main power supply to the chip.
These are the device outputs of PWM A and
PWM B respectively. These high current driver
outputs are capable of driving the gate of a power
FET. These outputs are actively held low when
Vcc is below the UVLO threshold.
Output voltage of LNB A and LNB B respectively.
Address pin to select two different addresses per
voltage level at this pin.
Error amp outputs used for compensation.
Feedback pins for respective PWMs
Charge pump connections.
When connected HIGH, this pin will change the
output of the respective PWM to 18V. Only
available on the QFN package option.
Functional Description
The ISL6405 dual output voltage regulator makes an ideal
choice for advanced satellite set-top box and personal video
recorder applications. Both supply and control voltage
outputs for two low-noise blocks (LNBs) are available
simultaneously in any output configuration. The device
utilizes built-in DC/DC step-converters that, from a single
supply source ranging from 8V to 14V, generate the voltages
that enable the linear post-regulators to work with a
minimum of dissipated power. An undervoltage lockout
circuit disables the circuit when VCC drops below a fixed
threshold (7.5V typ).
DiSEqC Encoding
The internal oscillator is factory-trimmed to provide a tone
of 22kHz in accordance with DiSEqC (EUTELSAT)
standards. No further adjustment is required. The 22kHz
oscillator can be controlled either by the I²C interface
(ENT1/2 bit) or by a dedicated pin (DSQIN1/2) that allows
immediate DiSEqC data encoding separately for each LNB.
(Please see Note 1 at the end of this section.) All the
functions of this IC are controlled via the I²C bus by writing
to the system registers (SR1, SR2). The same registers
can be read back, and two bits will report the diagnostic
status. The internal oscillator operates the converters at ten
times the tone frequency. The device offers full I²C
compatible functionality, 3.3V or 5V, and up to 400kHz
operation.
If the Tone Enable (ENT1/2) bit is set LOW through I²C, then
the DSQIN1/2 terminal activates the internal tone signal,
modulating the dc output with a 0.3V, 22kHz, symmetrical
waveform. The presence of this signal usually gives the LNB
information about the band to be received.
Burst coding of the 22kHz tone can be accomplished due to
the fast response of the DSQIN1/2 input and rapid tone
response. This allows implementation of the DiSEqC
(EUTELSAT) protocols.
When the ENT1/2 bit is set HIGH, a continuous 22kHz tone
is generated regardless of the DSQIN1/2 pin logic status for
the corresponding regulator channel (LNB-A or LNB-B). The
ENT1/2 bit must be set LOW when the DSQIN1 and/or
DSQIN2 pin is used for DiSEqC encoding.
Linear Regulator
The output linear regulator will sink and source current. This
feature allows full modulation capability into capacitive loads
as high as 0.25µF. In order to minimize the power
dissipation, the output voltage of the internal step-up
converter is adjusted to allow the linear regulator to work at
minimum dropout.
When the device is put in the shutdown mode (EN1,
EN2 = LOW), both PWM power blocks are disabled. (i.e.
when EN1 = 0, PWM1 is disabled, and when EN2 = 0,
PWM2 is disabled).
When the regulator blocks are active (EN1, EN2 = HIGH),
the output can be logic controlled to be 13V or 18V (typical)
by mean of the VSEL bit (Voltage Select) for remote
controlling of non-DiSEqC LNBs. Additionally, it is possible
to increment by 1V (typical) the selected voltage value to
compensate for the excess voltage drop along the coaxial
cable (LLC1/2 bit HIGH).
Output Timing
The programmed output voltage rise and fall times can be
set by an external capacitor. The output rise and fall times
will be approximately 3400 times the TCAP value. For the
recommended range of 0.47µF to 2.2µF, the rise and fall
time would be 1.6ms to 7.6ms. Using a 0.47µF capacitor
insures the PWM stays below its overcurrent threshold when
charging a 120µF VSW filter cap during the worst case 13V
to 19V transition. A typical value of 1.0µF is recommended.
7