ISL6294_07 Datasheet, PDF (7/9 Pages) Intersil Corporation – High Input Voltage Charger

ISL6294
Applications Information
Input Capacitor Selection
The input capacitor is required to suppress the power supply
transient response during transitions. Mainly this capacitor is
selected to avoid oscillation during the start up when the
input supply is passing the POR threshold and the VIN - BAT
comparator offset voltage. When the battery voltage is above
the POR threshold, the VIN - VBAT offset voltage dominates
the hysteresis value. Typically, a 1µF X5R ceramic capacitor
should be sufficient to suppress the power supply noise.
Output Capacitor Selection
The criteria for selecting the output capacitor is to maintain
the stability of the charger as well as to bypass any transient
load current. The minimum capacitance is a 1µF X5R
ceramic capacitor. The actual capacitance connected to the
output is dependent on the actual application requirement.
Charge Current Limit
The actual charge current in the CC mode is limited by
several factors in addition to the set I_REF. Figure 1 shows
three limits for the charge current in the CC mode. The
charge current is limited by the on resistance of the pass
element (power P-Channel MOSFET) if the input and the
output voltage are too close to each other. The solid curve
shows a typical case when the battery voltage is 4.0V and
the charge current is set to 700mA. The non-linearity on the
r_ON-limited region is due to the increased resistance at
higher die temperature. If the battery voltage increases to
higher than 4.0V, the entire curve moves towards right side.
As the input voltage increases, the charge current may be
reduced due to the thermal foldback function. The limit
caused by the thermal limit is dependent on the thermal
impedance. As the thermal impedance increases, the
thermal-limited curve moves towards left, as shown in
Figure 1.
700
r_ON
LIMITED
THERMAL
LIMITED
R_IREF
INCREASES
V_BAT
INCREASES
θ_JA or T_A
INCREASES
4.0
4.5
5.0
5.5
6.0
6.5
INPUT VOLTAGE (V)
FIGURE 1. CHARGE CURRENT LIMITS IN THE CC MODE
Layout Guidance
The ISL6294 uses a thermally-enhanced DFN package that
has an exposed thermal pad at the bottom side of the
package. The layout should connect as much as possible to
copper on the exposed pad. Typically the component layer is
more effective in dissipating heat. The thermal impedance
can be further reduced by using other layers of copper
connecting to the exposed pad through a thermal via array.
Each thermal via is recommended to have 0.3mm diameter
and 1mm distance from other thermal vias.
Input Power Sources
The input power source is typically a well-regulated wall
cube with 1-meter length wire or a USB port. The input
voltage ranges from 4.25V to 6.5V under full-load and
unloaded conditions. The ISL6294 can withstand up to 28V
on the input without damaging the IC. If the input voltage is
higher than typically 6.8V, the charger stops charging.
7
FN9174.4
July 9, 2007